Patents by Inventor Akihito Nishikawa

Akihito Nishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240168099
    Abstract: An estimation device is a device that estimates a charge state of an energy storage device including a negative electrode having a negative active material that contains Si. The estimation device includes a control unit that determines based on a charge-discharge history of the energy storage device whether or not to perform a first estimation method of estimating a charge state of the energy storage device by using a relationship between the charge state and a voltage of the energy storage device.
    Type: Application
    Filed: March 9, 2022
    Publication date: May 23, 2024
    Inventors: Shinnosuke ICHIKAWA, Shinya MIYAZONO, Akihito TANOI, Heisuke NISHIKAWA, Nobuhiro NAKAJIMA, Takashi SHIMIZU
  • Patent number: 7580849
    Abstract: A product sales supporting tool is provided where potential requirements for services accompanying product sales which will directly contribute to increased product sales, and systematic and easy formulation of product sales growth strategy are possible.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: August 25, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihito Nishikawa
  • Patent number: 6937913
    Abstract: Disclosed herein are a product design process and apparatus for quickly and easily defining an optimal product concept capable of conveying a high degree of customer satisfaction. In the process of the present invention, wants and needs information is analyzed, and, based on the analyzed wants and needs information, weighting is carried out with respect to evaluation indices which have been previously stored in a storage device and which are quantitative measures of the degree to which the user is likely to perceive a benefit latent in the product under consideration and inherent in the wants and needs information to have been achieved, an evaluation index having the highest weighting among a plurality of weighted evaluation indices is selected as a primary evaluation index and a product design concept for which the primary evaluation index selected is a maximum or minimum is defined.
    Type: Grant
    Filed: July 30, 2001
    Date of Patent: August 30, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihito Nishikawa, Yoshihiro Motowaki, Toshio Yonezawa
  • Publication number: 20040015387
    Abstract: A product sales supporting tool is provided where potential requirements for services accompanying product sales which will directly contribute to increased product sales, and systematic and easy formulation of product sales growth strategy are possible.
    Type: Application
    Filed: April 30, 2003
    Publication date: January 22, 2004
    Inventor: Akihito Nishikawa
  • Publication number: 20020077882
    Abstract: Disclosed herein are a product design process and apparatus for quickly and easily defining an optimal product concept capable of conveying a high degree of customer satisfaction, and for rapidly getting to market with a product having a high degree of market competitiveness.
    Type: Application
    Filed: July 30, 2001
    Publication date: June 20, 2002
    Inventors: Akihito Nishikawa, Yoshihiro Motowaki, Toshio Yonezawa
  • Patent number: 5586263
    Abstract: A data communication control device controls data transmission between a network bus and a system bus. The data communication control device includes a network bus interface connected to the network bus, a system bus interface connected to the system bus. A port 1 of the two-port memory in an FIFo/RAM is connected to the network bus interface, microprocessor, direct memory access through a first bus. A port 2 of the two-port memory in the FIFo/RAM is connected to the direct memory access through a second bus. The microprocessor is connected to the system bus interface through a third bus. The direct memory access is connected to the system bus interface through a fourth bus.
    Type: Grant
    Filed: February 1, 1993
    Date of Patent: December 17, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiichi Katsumata, Koichi Tanaka, Toshiyuki Yaguchi, Akira Kanuma, Akihito Nishikawa
  • Patent number: 5208831
    Abstract: It is an object of this invention to provide a novel network interface system which is able to connect automatically to the respective network stations having different data transfer speeds, in order to avoid the above problems. According to this invention, there is provided a detector and a selector in the communication interface to automatically select the appropriate data transfer speed. In the above structure, the speed of communication data transferred by a network is one of two detected by the detector which is able to detect a transfer speed and provide outputs at a first level signal when the transfer speed is at one level and outputs a second level signal when it is at a second level. The selecting means selects the frequency to connect a network station in response to the signal output from the detector. As a result, users need not select the module by themselves, the system automatically select the module.
    Type: Grant
    Filed: February 3, 1992
    Date of Patent: May 4, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaji Ueno, Akihito Nishikawa, Shinichi Iida, Hajime Shiraishi
  • Patent number: 5021950
    Abstract: A multiprocessor system is comprised of a bus and a plurality of processor modules. Each processor module includes a bus arbitration block, a bus access control block, an address output block, a data input/output block, a clock signal generating block, a stop request block for requesting the stop of supplying a clock signal, an operation processing block for processing data, and a stop control block. The stop control block stores the contents of the bus access (a type of the bus, the address and data concerning the access, etc.) as is made by the operation processing block when the clock signal is stopped, and to what clock of that access cycle the bus access proceeds. The stop control block controls the bus arbitration block to electrically disconnect the processor module from the bus. After the restart of supplying the clock signal, the bus arbitration block, the bus access control block, the address output block and the data input/output block are restored on the basis of the contents of the bus access.
    Type: Grant
    Filed: December 12, 1985
    Date of Patent: June 4, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihito Nishikawa