Patents by Inventor Akihito Yamamoto
Akihito Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8324679Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.Type: GrantFiled: March 26, 2012Date of Patent: December 4, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Ichige, Fumitaka Arai, Riichiro Shirota, Toshitake Yaegashi, Yoshio Ozawa, Akihito Yamamoto, Ichiro Mizushima, Yoshihiko Saito
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Patent number: 8278697Abstract: A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, the second insulating film including a lower silicon nitride film, a lower silicon oxide film formed on the lower silicon nitride film, an intermediate insulating film formed on the lower silicon oxide film and containing a metal element, the intermediate insulating film having a relative dielectric constant of greater than 7, an upper silicon oxide film formed on the intermediate insulating film, and an upper silicon nitride film formed on the upper silicon oxide film.Type: GrantFiled: January 17, 2012Date of Patent: October 2, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Tanaka, Daisuke Nishida, Ryota Fujitsuka, Katsuyuki Sekine, Akihito Yamamoto, Katsuaki Natori, Yoshio Ozawa
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Publication number: 20120181598Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.Type: ApplicationFiled: March 26, 2012Publication date: July 19, 2012Inventors: Masayuki ICHIGE, Fumitaka Arai, Riichiro Shirota, Toshitake Yaegashi, Yoshio Ozawa, Akihito Yamamoto, Ichiro Mizushima, Yoshihiko Saito
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Publication number: 20120112263Abstract: A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, the second insulating film including a lower silicon nitride film, a lower silicon oxide film formed on the lower silicon nitride film, an intermediate insulating film formed on the lower silicon oxide film and containing a metal element, the intermediate insulating film having a relative dielectric constant of greater than 7, an upper silicon oxide film formed on the intermediate insulating film, and an upper silicon nitride film formed on the upper silicon oxide film.Type: ApplicationFiled: January 17, 2012Publication date: May 10, 2012Inventors: Masayuki Tanaka, Daikuse Nishida, Ryota Fujitsuka, Katsuyuki Sekine, Akihito Yamamoto, Katsuaki Natori, Yoshio Ozawa
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Patent number: 8114755Abstract: A method of manufacturing a semiconductor device includes removing a part of a semiconductor substrate to form a protruding portion and a recess portion in a surface area of the semiconductor substrate, forming a first epitaxial semiconductor layer in the recess portion, forming a second epitaxial semiconductor layer on the protruding portion and the first epitaxial semiconductor layer, removing a first part of the second epitaxial semiconductor layer with a second part of the second epitaxial semiconductor layer left to expose a part of the first epitaxial semiconductor layer, and etching the first epitaxial semiconductor layer from the exposed part of the first epitaxial semiconductor layer to form a cavity under the second part of the second epitaxial semiconductor layer.Type: GrantFiled: June 25, 2008Date of Patent: February 14, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Ichiro Mizushima, Yoshio Ozawa, Takashi Nakao, Akihito Yamamoto, Takashi Suzuki, Masahiro Kiyotoshi, Minako Inukai, Kaori Umezawa, Hiroaki Yamada
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Patent number: 8110865Abstract: A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, the second insulating film including a lower silicon nitride film, a lower silicon oxide film formed on the lower silicon nitride film, an intermediate insulating film formed on the lower silicon oxide film and containing a metal element, the intermediate insulating film having a relative dielectric constant of greater than 7, an upper silicon oxide film formed on the intermediate insulating film, and an upper silicon nitride film formed on the upper silicon oxide film.Type: GrantFiled: September 22, 2010Date of Patent: February 7, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Tanaka, Daisuke Nishida, Ryota Fujitsuka, Katsuyuki Sekine, Akihito Yamamoto, Katsuaki Natori, Yoshio Ozawa
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Publication number: 20110294304Abstract: A method of manufacturing a semiconductor device comprising a first insulating film formed on a semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, forming the second insulating film comprises forming a lower insulating film containing oxygen and a metal element, thermally treating the lower insulating film in an atmosphere containing oxidizing gas, and forming an upper insulating film on the thermally treated lower insulating film using film forming gas containing at least one of hydrogen and chlorine.Type: ApplicationFiled: August 8, 2011Publication date: December 1, 2011Inventors: Yoshio Ozawa, Akihito Yamamoto
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Publication number: 20110272745Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.Type: ApplicationFiled: July 19, 2011Publication date: November 10, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Masahiro Kiyotoshi, Akihito Yamamoto, Yoshio Ozawa, Fumitaka Arai, Riichiro Shirota
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Publication number: 20110228289Abstract: An inkjet printer A includes: a casing 6 having an output port 47 through which printing paper P1, P2 after printing is output to outside the casing 6; a drying chamber 71 provided downstream, in a paper conveyance direction, of a print head H on a conveyance path in the casing 6, and communicating with the output port 47; and a dryer 72 configured to blow, into the drying chamber 71, dry wind W for drying ink on the printing paper P1, P2 after printing. The dryer 72 is configured to blow the dry wind W downstream in the paper conveyance direction in the drying chamber 72. Dry wind W from the dryer 72 is blown to outside the casing 6 through the output port 47.Type: ApplicationFiled: July 14, 2008Publication date: September 22, 2011Applicant: NORITSU KOKI CO., LTD.Inventors: Akihito Yamamoto, Yoshihisa Higashimoto, Nobuaki Nakaoka, Hideya Miyazaki
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Patent number: 8017989Abstract: A nonvolatile semiconductor memory device including a semiconductor substrate having a semiconductor layer and an insulating material provided on a surface thereof, a surface of the insulating material is covered with the semiconductor layer, and a plurality of memory cells provided on the semiconductor layer, the memory cells includes a first dielectric film provided by covering the surface of the semiconductor layer, a plurality of charge storage layers provided above the insulating material and on the first dielectric film, a plurality of second dielectric films provided on the each charge storage layer, a plurality of conductive layers provided on the each second dielectric film, and an impurity diffusion layer formed partially or overall at least above the insulating material and inside the semiconductor layer and at least a portion of a bottom end thereof being provided by an upper surface of the insulating material.Type: GrantFiled: March 17, 2010Date of Patent: September 13, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yoshio Ozawa, Ichiro Mizushima, Takashi Nakao, Akihito Yamamoto, Takashi Suzuki, Masahiro Kiyotoshi
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Patent number: 8008732Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.Type: GrantFiled: September 20, 2007Date of Patent: August 30, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masahiro Kiyotoshi, Akihito Yamamoto, Yoshio Ozawa, Fumitaka Arai, Riichiro Shirota
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Patent number: 8008152Abstract: A method of manufacturing a semiconductor device comprising a first insulating film formed on a semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, forming the second insulating film comprises forming a lower insulating film containing oxygen and a metal element, thermally treating the lower insulating film in an atmosphere containing oxidizing gas, and forming an upper insulating film on the thermally treated lower insulating film using film forming gas containing at least one of hydrogen and chlorine.Type: GrantFiled: March 29, 2007Date of Patent: August 30, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Ryota Fujitsuka, Katsuaki Natori, Daisuke Nishida, Masayuki Tanaka, Katsuyuki Sekine, Yoshio Ozawa, Akihito Yamamoto
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Patent number: 7999304Abstract: A semiconductor device includes a semiconductor substrate, and nonvolatile memory cells, each of the cells including a channel region having a channel length and a channel width, a tunnel insulating film, a floating gate electrode, a control gate electrode, an inter-electrode insulating film between the floating and control gate electrodes, and an electrode side-wall insulating film on side-wall surfaces of the floating and control gate electrodes, the electrode side-wall insulating film including first and second insulating films having first and second dielectric constants, the first dielectric constant being higher than the second dielectric constant, the second dielectric constant being higher than a dielectric constant of a silicon nitride film, the first insulating film being in a central region of a facing region between the floating and control gate electrodes, the second insulating region being in the both end regions of the facing region and protruding from the both end portions.Type: GrantFiled: February 6, 2008Date of Patent: August 16, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yoshio Ozawa, Akihito Yamamoto, Katsuaki Natori, Masayuki Tanaka, Katsuyuki Sekine, Daisuke Nishida, Ryota Fujitsuka
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Patent number: 7982259Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.Type: GrantFiled: March 19, 2007Date of Patent: July 19, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Ichige, Fumitaka Arai, Riichiro Shirota, Toshitake Yaegashi, Yoshio Ozawa, Akihito Yamamoto, Ichiro Mizushima, Yoshihiko Saito
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Patent number: 7954939Abstract: A decurling mechanism for performing a decurling process of correcting the curl of paper includes: a first roller; a second roller disposed travelably around the first roller; and a roller position changing mechanism for changing the second roller to a plurality of positions set on a traveling path of the second roller. The plurality of positions include a decurling position in which the decurling process to the paper is enabled and the paper is conveyed while being pinched between the first and second rollers, a conveyance position in which the decurling process to the paper is disabled and the paper is conveyed while being pinched between the first and second rollers and a pinch release position in which the paper is released from the pinch between the first and second rollers.Type: GrantFiled: January 27, 2009Date of Patent: June 7, 2011Assignee: Noritsu Koki Co., Ltd.Inventors: Akihito Yamamoto, Yoshitsugu Tokai
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Publication number: 20110108905Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.Type: ApplicationFiled: January 14, 2011Publication date: May 12, 2011Inventors: Masayuki ICHIGE, Fumitaka Arai, Riichiro Shirota, Toshitake Yaegashi, Yoshio Ozawa, Akihito Yamamoto, Ichiro Mizushima, Yoshihiko Saito
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Patent number: 7927949Abstract: A semiconductor memory device manufacturing method includes forming a floating gate electrode above a semiconductor substrate, forming an interelectrode insulating film above the floating gate electrode, forming a first radical nitride film on a surface of the interelectrode insulating film by first radical nitriding, and forming a control gate electrode on the first radical nitride film.Type: GrantFiled: April 7, 2010Date of Patent: April 19, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yoshio Ozawa, Isao Kamioka, Junichi Shiozawa, Akihito Yamamoto, Ryota Fujitsuka, Yoshihiro Ogawa, Katsuaki Natori, Katsuyuki Sekine, Masayuki Tanaka, Daisuke Nishida
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Patent number: 7888730Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.Type: GrantFiled: March 19, 2007Date of Patent: February 15, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Ichige, Fumitaka Arai, Riichiro Shirota, Toshitake Yaegashi, Yoshio Ozawa, Akihito Yamamoto, Ichiro Mizushima, Yoshihiko Saito
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Publication number: 20110012190Abstract: A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, the second insulating film including a lower silicon nitride film, a lower silicon oxide film formed on the lower silicon nitride film, an intermediate insulating film formed on the lower silicon oxide film and containing a metal element, the intermediate insulating film having a relative dielectric constant of greater than 7, an upper silicon oxide film formed on the intermediate insulating film, and an upper silicon nitride film formed on the upper silicon oxide film.Type: ApplicationFiled: September 22, 2010Publication date: January 20, 2011Inventors: Masayuki Tanaka, Daisuke Nishida, Ryota Fujitsuka, Katsuyuki Sekine, Akihito Yamamoto, Katsuaki Natori, Yoshio Ozawa
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Patent number: 7803682Abstract: A semiconductor memory device includes a plurality of memory transistors. Each of the memory transistors has: a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The floating gate electrode includes, in a cross section taken along a bit line direction, a first conductive film, first sidewall insulating films opposed to each other across the first conductive film, and a second conductive film provided on the first sidewall insulating films and the first conductive film. The interelectrode insulating film is provided on the second conductive film. The control gate electrode includes a third conductive film provided on the interelectrode insulating film and a fourth conductive film provided on the third conductive film.Type: GrantFiled: August 21, 2007Date of Patent: September 28, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Katsuaki Natori, Masayuki Tanaka, Akihito Yamamoto