Patents by Inventor Akiko Tsukamoto
Akiko Tsukamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10449862Abstract: Cell voltage measurement is executed immediately after termination of diagnosis on a cell voltage detection function. In a battery managing device 10, a voltage detecting unit 140 detects a terminal voltage of each of battery cells 21 and 22. An RC filter 110 is electrically connected to voltage detecting lines L1, L2, and L3, and a status variation causing unit 130 causes an electrical status variation with respect to the voltage detecting lines L1, L2, and L3. A voltage fluctuating unit 120 fluctuates the terminal voltage of the battery cells 21 and 22 in response to the electrical status variation that is caused by the status variation causing unit 130. A microcomputer 150 diagnoses the voltage detecting unit 140 on the basis of a detection result of the terminal voltage of the battery cells 21 and 22 by the voltage detecting unit 140 when the terminal voltage of the battery cells 21 and 22 is fluctuated by the voltage fluctuating unit 120.Type: GrantFiled: March 4, 2016Date of Patent: October 22, 2019Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.Inventors: Tomonori Kanai, Akihiko Kudo, Tomoyuki Arima, Akiko Tsukamoto
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Patent number: 10393823Abstract: An object is to achieve management control of an assembled battery using an accurate measured value of a cell voltage. A battery system monitoring apparatus 10 that monitors and controls a battery system includes battery monitoring circuits 100 provided for respective cell groups 120. Each of the battery monitoring circuits 100 includes a cell voltage measurement module 6 that is connected with two electrodes of respective single battery cells 110 of a corresponding cell group 120 via voltage detection lines 2 and that measures a cell voltage of each of the single battery cells 110 at each of predetermined timings. An RC filter 4 is connected with the voltage detection lines 2. The RC filter 4 includes resistors and capacitors. The cell voltage measurement module 6 extends intervals at which the cell voltage is to be measured when a stored charge amount in the capacitor in the RC filter 4 changes.Type: GrantFiled: February 3, 2016Date of Patent: August 27, 2019Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.Inventors: Akihiko Kudo, Tomonori Kanai, Tomoyuki Arima, Akiko Tsukamoto
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Patent number: 10386419Abstract: Measurement of a cell voltage is executed immediately after diagnosis of a battery management device is ended. In a battery management device, current sources repeatedly perform an energization operation to cause a current to flow to voltage detection lines with a magnitude of the current that enables each amount of charge stored in capacitors changed by one energization operation to fall within a range corresponding to a fluctuation width of terminal voltages of battery cells during the energization operation when resistors are in a normal state. When the difference between the current terminal voltage of the battery cell and the past terminal voltage of the battery cell is larger than the predetermined threshold value, the microcomputer diagnoses that the resistor is in the open state.Type: GrantFiled: March 4, 2016Date of Patent: August 20, 2019Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.Inventors: Tomonori Kanai, Akihiko Kudo, Tomoyuki Arima, Akiko Tsukamoto
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Publication number: 20180052207Abstract: Measurement of a cell voltage is executed immediately after diagnosis of a battery management device is ended. In a battery management device, current sources repeatedly perform an energization operation to cause a current to flow to voltage detection lines with a magnitude of the current that enables each amount of charge stored in capacitors changed by one energization operation to fall within a range corresponding to a fluctuation width of terminal voltages of battery cells during the energization operation when resistors are in a normal state. When the difference between the current terminal voltage of the battery cell and the past terminal voltage of the battery cell is larger than the predetermined threshold value, the microcomputer diagnoses that the resistor is in the open state.Type: ApplicationFiled: March 4, 2016Publication date: February 22, 2018Applicant: HITACHI AUTOMOTIVE SYSTEMS, LTD.Inventors: Tomonori KANAI, Akihiko KUDO, Tomoyuki ARIMA, Akiko TSUKAMOTO
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Publication number: 20180043781Abstract: Cell voltage measurement is executed immediately after termination of diagnosis on a cell voltage detection function. In a battery managing device 10, a voltage detecting unit 140 detects a terminal voltage of each of battery cells 21 and 22. An RC filter 110 is electrically connected to voltage detecting lines L1, L2, and L3, and a status variation causing unit 130 causes an electrical status variation with respect to the voltage detecting lines L1, L2, and L3. A voltage fluctuating unit 120 fluctuates the terminal voltage of the battery cells 21 and 22 in response to the electrical status variation that is caused by the status variation causing unit 130. A microcomputer 150 diagnoses the voltage detecting unit 140 on the basis of a detection result of the terminal voltage of the battery cells 21 and 22 by the voltage detecting unit 140 when the terminal voltage of the battery cells 21 and 22 is fluctuated by the voltage fluctuating unit 120.Type: ApplicationFiled: March 4, 2016Publication date: February 15, 2018Applicant: HITACHI AUTOMOTIVE SYSTEMS, LTD.Inventors: Tomonori KANAI, Akihiko KUDO, Tomoyuki ARIMA, Akiko TSUKAMOTO
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Publication number: 20180017631Abstract: An object is to achieve management control of an assembled battery using an accurate measured value of a cell voltage. A battery system monitoring apparatus 10 that monitors and controls a battery system includes battery monitoring circuits 100 provided for respective cell groups 120. Each of the battery monitoring circuits 100 includes a cell voltage measurement module 6 that is connected with two electrodes of respective single battery cells 110 of a corresponding cell group 120 via voltage detection lines 2 and that measures a cell voltage of each of the single battery cells 110 at each of predetermined timings. An RC filter 4 is connected with the voltage detection lines 2. The RC filter 4 includes resistors and capacitors. The cell voltage measurement module 6 extends intervals at which the cell voltage is to be measured when a stored charge amount in the capacitor in the RC filter 4 changes.Type: ApplicationFiled: February 3, 2016Publication date: January 18, 2018Applicant: HITACHI AUTOMOTIVE SYSTEMS, LTD.Inventors: Akihiko KUDO, Tomonori KANAI, Tomoyuki ARIMA, Akiko TSUKAMOTO
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Patent number: 8604589Abstract: Provided is a method capable of forming a polycrystalline silicon resistor with preferable ratio accuracy so as to design a resistor circuit with high accuracy. In the method, a length of a low concentration impurity region constituting the polycrystalline silicon resistor in a longitudinal direction is varied in accordance with an occupying area of a metal portion overlapping the low concentration impurity region, thereby correcting a variation in resistance without varying an external shape and the occupying area of the resistor.Type: GrantFiled: July 26, 2006Date of Patent: December 10, 2013Assignee: Seiko Instruments Inc.Inventors: Akiko Tsukamoto, Hirofumi Harada
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Patent number: 8242580Abstract: Provided is a method which is capable of producing polycrystalline silicon resistors with a high ratio accuracy so that a precision resistor circuit may be designed. A semiconductor device has a structure in which an occupation area of a metal portion covering a low concentration impurity region constituting each of the polycrystalline silicon resistors is adjusted so that ratio accuracy may be further corrected after a resistance is corrected.Type: GrantFiled: February 4, 2010Date of Patent: August 14, 2012Assignee: Seiko Epson Instruments Inc.Inventor: Akiko Tsukamoto
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Patent number: 7829354Abstract: Deviation occurring in a particular region in a plane of a resistor group which constitutes a semiconductor integrated circuit is improved and a quick increase in yield is accomplished. Provided is a fuse trimming method for a semiconductor device in which circuit elements such as transistors and resistors are formed on a semiconductor wafer and which has fuse elements capable of adjusting a resistance value of the resistors by laser trimming, including a resistor correction step of correcting in the particular region of the semiconductor wafer the resistance value of the resistors based on an amount of deviation from a target value of the resistance value of the resistors.Type: GrantFiled: February 11, 2008Date of Patent: November 9, 2010Assignee: Seiko Instruments Inc.Inventors: Akiko Tsukamoto, Jun Osanai
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Patent number: 7790555Abstract: A semiconductor device manufacturing method includes a field oxide insulation film forming step, an electrode forming step, and a resistor forming step. The field oxide insulation film forming step comprises forming a field oxide insulation film on a surface of the semiconductor substrate so that a portion which corresponds to a side surface portion for each of active regions formed on the surface of the semiconductor substrate, which opposes a rotation center of the surface of the semiconductor substrate in spin-coating of a photoresist in the electrode forming step, and which is located at a front side of a centrifugal force acting direction along the surface of the semiconductor substrate has a curved surface that is convex in a forward direction of the centrifugal force along the surface of the semiconductor substrate as seen in plan view of the semiconductor substrate.Type: GrantFiled: May 21, 2007Date of Patent: September 7, 2010Assignee: Seiko Instruments Inc.Inventors: Akiko Tsukamoto, Hisashi Hasegawa, Jun Osanai
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Publication number: 20100200952Abstract: Provided is a method which is capable of producing polycrystalline silicon resistors with a high ratio accuracy so that a precision resistor circuit may be designed. A semiconductor device has a structure in which an occupation area of a metal portion covering a low concentration impurity region constituting each of the polycrystalline silicon resistors is adjusted so that ratio accuracy may be further corrected after a resistance is corrected.Type: ApplicationFiled: February 4, 2010Publication date: August 12, 2010Inventor: Akiko Tsukamoto
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Patent number: 7737027Abstract: Exuding of a interconnecting material to a substrate, which occurs because of a thinned state of and a beak in a barrier metal layer is prevented, irrespective of a laminated state of the barrier metal layer. In the present invention, a protective layer is formed on a side wall by using an insulating film or the like after the deposition of the barrier metal layer, whereby the interconnecting material can be prevented from exuding to the substrate due to influence of heat treatment such as alloying, irrespective of the laminated state of the side wall of the contact hole and the barrier metal layer. Further, the formation of the protective layer allows the side wall to be smoother to thereby improve coverage of the interconnecting material at the same time.Type: GrantFiled: August 27, 2008Date of Patent: June 15, 2010Assignee: Seiko Instruments Inc.Inventors: Akiko Tsukamoto, Jun Osanai
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Publication number: 20090061620Abstract: Exuding of a interconnecting material to a substrate, which occurs because of a thinned state of and a beak in a barrier metal layer is prevented, irrespective of a laminated state of the barrier metal layer. In the present invention, a protective layer is formed on a side wall by using an insulating film or the like after the deposition of the barrier metal layer, whereby the interconnecting material can be prevented from exuding to the substrate due to influence of heat treatment such as alloying, irrespective of the laminated state of the side wall of the contact hole and the barrier metal layer. Further, the formation of the protective layer allows the side wall to be smoother to thereby improve coverage of the interconnecting material at the same time.Type: ApplicationFiled: August 27, 2008Publication date: March 5, 2009Inventors: Akiko Tsukamoto, Jun Osanai
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Publication number: 20080248601Abstract: Deviation occurring in a particular region in a plane of a resistor group which constitutes a semiconductor integrated circuit is improved and a quick increase in yield is accomplished. Provided is a fuse trimming method for a semiconductor device in which circuit elements such as transistors and resistors are formed on a semiconductor wafer and which has fuse elements capable of adjusting a resistance value of the resistors by laser trimming, including a resistor correction step of correcting in the particular region of the semiconductor wafer the resistance value of the resistors based on an amount of deviation from a target value of the resistance value of the resistors.Type: ApplicationFiled: February 11, 2008Publication date: October 9, 2008Inventors: Akiko Tsukamoto, Jun Osanai
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Publication number: 20070272984Abstract: Provided is a semiconductor device manufacturing method including a field oxide insulation film forming step including forming a field oxide insulation film (12) so that, in an active region (13), a portion (13a), which corresponds to a side surface portion of the active region (13) opposing a rotation center (O) in spin-coating on the surface of the semiconductor substrate (11) in a centrifugal force acting direction (F) along the surface of the semiconductor substrate (11) and located in a forward side of the centrifugal force acting direction (F), has a curved surface convex to the forward side of the centrifugal force acting direction (F) when the semiconductor substrate (11) is seen in a plan view.Type: ApplicationFiled: May 21, 2007Publication date: November 29, 2007Inventors: Akiko Tsukamoto, Hisashi Hasegawa, Jun Osanai
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Publication number: 20070023844Abstract: Provided is a method capable of forming a polycrystalline silicon resistor with preferable ratio accuracy so as to design a resistor circuit with high accuracy. In the method, a length of a low concentration impurity region constituting the polycrystalline silicon resistor in a longitudinal direction is varied in accordance with an occupying area of a metal portion overlapping the low concentration impurity region, thereby correcting a variation in resistance without varying an external shape and the occupying area of the resistor.Type: ApplicationFiled: July 26, 2006Publication date: February 1, 2007Inventors: Akiko Tsukamoto, Hirofumi Harada
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Patent number: D1026087Type: GrantFiled: January 20, 2023Date of Patent: May 7, 2024Assignee: PLUS CorporationInventors: Atsushi Tsukamoto, Akiko Tanaka, Sari Hiraoka, Hayato Horie