Abstract: A microcomputer includes a CPU capable of performing a plurality of tasks in a parallel time-sharing operation. The tasks include at least one special task having a fixed loop program with a constant increase of an instruction address. When the CPU performs a conditional judgment instruction in the special task, the CPU prohibits reflecting an execution result of the conditional judgment instruction to both of the CPU and a periphery circuit in a case where it is no need to perform an instruction described in the special task after the conditional judgment instruction.

Abstract: A signal processing apparatus for processing a periodic signal outputted from a signal source has a central processing unit and a task switch timer. The central processing unit performs multiple tasks including a signal processing task in parallel. In the signal processing task, the central processing unit starts to process the periodic signal after performing a synchronization processing to synchronize with the periodic signal, setting the task switch timer to a predetermined time upon completion of the synchronization processing, and enabling an interrupt to the central processing unit upon completion of the synchronization processing. The task switch timer disables the interrupt to the central processing unit immediately before expiring. The task switch timer outputs a task switch signal to the central processing unit when expiring, so that the central processing unit switches to the signal processing task.

Abstract: It is determined that a write access is executed to a stack area of a main memory. It is then determined whether another write access to a corresponding access destination address in the stack area occurred in the past by referring to an access flag table. In contrast, it is determined that a write access is executed to a global area of the main memory. It is then determined whether another write access to a corresponding access destination address in the global area occurred in the past with referring to an access list. Such a configuration can efficiently provide individual advantages of the determination methods using both the access flag table and the address list. The presence or absence of the past saving execution can be efficiently determined at the time of write access.

Abstract: Provided is a moving body detecting apparatus capable of detecting only a body to be notified without detecting a body similar in feature to the body to be notified. To confirm whether a break-in body appears in static images from a camera, the apparatus sets a monitoring region for monitoring a window portion in the static images and a monitoring region for monitoring a door body portion therein, and produces difference images from the static images. A pixel set existing in common to the difference images continuing in time sequence is extracted from an image composed so that pixel values reach a maximum. On the basis of the motion vector, a decision is made as to whether the movement of the pixel set from the window portion to the door body portion occurs or not.

Abstract: A microprocessor which is adapted to start a second task at a predetermined time when a first task is running if a current time becomes to be equal to the predetermined time is disclosed. The microprocessor executing an instruction read out from a program address updated every time when each execution of instruction is completed, includes update ceasing means for ceasing the program address from being updated when an stopping time comes in order to abort a first task defined by a first computer program and overwriting means for overwriting the program address with an initial address of a second computer program when a predetermined time comes in order to start to execute a second task defined by the second computer program at the predetermined time.

Abstract: A microcomputer includes a CPU capable of performing a plurality of tasks in a parallel time-sharing operation. The tasks include at least one special task having a fixed loop program with a constant increase of an instruction address. When the CPU performs a conditional judgement instruction in the special task, the CPU prohibits reflecting an execution result of the conditional judgement instruction to both of the CPU and a periphery circuit in a case where it is no need to perform an instruction described in the special task after the conditional judgement instruction.

Abstract: A method is provided for correcting lightness of an image using a multiscale retinex. Lightness of a subject pixel of an original image is corrected using a convolution operation of a surround function and surround pixels with respect to the subject pixel of the original image, and the convolution operation is performed over a plurality of scales. The surround function has a simplified model such that a value of the surround function is changed in a stepwise way along two axes orthogonal to each other.

Abstract: In a memory controller, a serial data including an instruction bit train with addition of a start bit, a clock signal, a chip enable signal, and a reset signal are inputted. During the active period in which the chip enable signal is being inputted, the serial data is stored depending on the clock signal and an enabling signal is generated based on the end timing of active period. Thereby, memory access is executed depending on contents of the instruction bit train. However, when the relevant apparatus is reset during the active period, generation of the enabling signal based on the end timing of the active period is inhibited.

Abstract: A memory control apparatus for controlling the operation of a memory array in a serial memory employs a command control section for registering the bits of an instruction which is received as an externally supplied set of serial data in conjunction with a corresponding series of cycles of a clock signal, with each set of serial data formatted as a command data portion preceded by a start bit, whereby the shifting of the start bit into the MSB stage of the shift register is detected and used to terminate supplying the clock signal to the shift register, thereby eliminating the use of a counter circuit. Any additional clock signal cycle following shifting of the start bit into the MSB stage of the shift register is detected, so that operating errors caused by noise in the received clock signal can be reliably eliminated.

Abstract: A method for correcting lightness of an image includes the steps of: calculating a first scale and a second scale based on an image scale of an original image from image information of the original image; multiscale retinex processing the original image with respect to the first scale and the second scale; and synthesizing a result of the multiscale retinex processing with the image information of the original image.

Abstract: Provided is a moving body detecting apparatus capable of detecting only a body to be notified without detecting a body similar in feature to the body to be notified. To confirm whether a break-in body appears in static images from a camera, the apparatus sets a monitoring region for monitoring a window portion in the static images and a monitoring region for monitoring a door body portion therein, and produces difference images from the static images. A pixel set existing in common to the difference images continuing in time sequence is extracted from an image composed so that pixel values reach a maximum. On the basis of the motion vector, a decision is made as to whether the movement of the pixel set from the window portion to the door body portion occurs or not.

Abstract: In a memory controller, a serial data including an instruction bit train with addition of a start bit, a clock signal, a chip enable signal, and a reset signal are inputted. During the active period in which the chip enable signal is being inputted, the serial data is stored depending on the clock signal and an enabling signal is generated based on the end timing of active period. Thereby, memory access is executed depending on contents of the instruction bit train. However, when the relevant apparatus is reset during the active period, generation of the enabling signal based on the end timing of the active period is inhibited.

Abstract: A memory control apparatus for controlling the operation of a memory array in a serial memory such as a serial EEPROM employs a command control section for registering in a shift register the bits of an instruction which is received as an externally supplied set of serial data in conjunction with a corresponding series of cycles of a clock signal, with each set of serial data formatted as a command data portion preceded by a start bit, whereby the shifting of the start bit into the MSB stage of the shift register is detected and used to terminate supplying the clock signal to the shift register, thereby eliminating the use of a counter circuit for such clock signal control.