Abstract: A memory system includes a nonvolatile memory, and a controller including an equalizer circuit and a clock-and-data output circuit. The equalizer circuit receives a first data signal from a host via a serial communication, reduces an inter-symbol interference jitter of the first data signal to generate a second data signal, and outputs the second data signal. The clock-and-data output circuit extracts a third data signal and a clock signal from the second data signal and outputs the third data signal and the clock signal. The controller executes, when a link speed with the host is switched, a process of detecting predetermined data in the third data signal based on the first data signal received from the host, and resets a state of the clock-and-data output circuit when the predetermined data is not detected within a predetermined period of time.

Abstract: A memory system includes a nonvolatile memory, and a controller including an equalizer circuit and a clock-and-data output circuit. The equalizer circuit receives a first data signal from a host via a serial communication, reduces an inter-symbol interference jitter of the first data signal to generate a second data signal, and outputs the second data signal. The clock-and-data output circuit extracts a third data signal and a clock signal from the second data signal and outputs the third data signal and the clock signal. The controller executes, when a link speed with the host is switched, a process of detecting predetermined data in the third data signal based on the first data signal received from the host, and resets a state of the clock-and-data output circuit when the predetermined data is not detected within a predetermined period of time.

Abstract: According to one embodiment, in a first state, a control circuit determines, based on first information and second information, information on a request that includes a setting of a transmission circuit of a host to be set as an initial setting in a second state. The first state is a state of communicating with a host at a first communication speed conforming to a first specification. The second state is a state of communicating with the host at a second communication speed conforming to a second specification. The second communication speed is different from the first communication speed. The first information is information on a request of a setting of the transmission circuit of the host. The second information is information on a quality of a signal received by a reception circuit, which has been transmitted from the transmission circuit of the host.

Abstract: According to one embodiment, in a first state, a control circuit determines, based on first information and second information, information on a request that includes a setting of a transmission circuit of a host to be set as an initial setting in a second state. The first state is a state of communicating with a host at a first communication speed conforming to a first specification. The second state is a state of communicating with the host at a second communication speed conforming to a second specification. The second communication speed is different from the first communication speed. The first information is information on a request of a setting of the transmission circuit of the host. The second information is information on a quality of a signal received by a reception circuit, which has been transmitted from the transmission circuit of the host.

Abstract: A memory system includes a nonvolatile semiconductor memory, and a controller circuit that includes a physical layer and is configured to store information defining a plurality of low power consumption modes for setting the physical layer to a low power consumption state while controlling the physical layer according to a first standard, and control input and output of signals between the physical layer and the nonvolatile semiconductor memory according to a second standard. The controller circuit selects one of the low power consumption modes based on a data transfer state of the physical layer.

Abstract: An electronic device is connectable with a host via a serial interface including a link configured with a plurality of lanes, each of which includes a differential signal wire pair for transmission and a differential signal wire pair for reception. The electronic device includes a plurality of transmitter circuits that respectively transmit data via the differential signal wire pair for transmission of each of the corresponding lanes, a plurality of receiver circuits that respectively receive data via the differential signal wire pair for reception of each of the corresponding lanes, and a control circuit. The control circuit causes a state of the electronic device to transition from a normal operation state to a state in which the plurality of transmitter circuits are maintained in an active state and the plurality of receiver circuits are in an inactive state except for one receiver circuit corresponding to one of the lanes.

Abstract: A memory system includes a nonvolatile semiconductor memory, and a controller circuit that includes a physical layer and is configured to store information defining a plurality of low power consumption modes for setting the physical layer to a low power consumption state while controlling the physical layer according to a first standard, and control input and output of signals between the physical layer and the nonvolatile semiconductor memory according to a second standard. The controller circuit selects one of the low power consumption modes based on a data transfer state of the physical layer.

Abstract: An electronic device is connectable with a host via a serial interface including a link configured with a plurality of lanes, each of which includes a differential signal wire pair for transmission and a differential signal wire pair for reception. The electronic device includes a plurality of transmitter circuits that respectively transmit data via the differential signal wire pair for transmission of each of the corresponding lanes, a plurality of receiver circuits that respectively receive data via the differential signal wire pair for reception of each of the corresponding lanes, and a control circuit. The control circuit causes a state of the electronic device to transition from a normal operation state to a state in which the plurality of transmitter circuits are maintained in an active state and the plurality of receiver circuits are in an inactive state except for one receiver circuit corresponding to one of the lanes.