Abstract: A HUD 1 comprises an image display device 30 including an LCD panel 31c, a virtual image optical system 40 forming an optical path L of an image light emitted from the LCD panel, and an outer housing 50 wherein: the outer housing includes an outer case 51 accommodating the virtual image optical system and having the image display device attached thereto, an upper cover 52 covering an upper portion from which the image light is emitted in the outer case, and a bottom cover 60 covering a bottom portion of the outer case; the bottom cover accommodates the image display device and the bottom surface of the outer case when fixed to the outer case such that the image display device to isolate them form an external space of the outer housing; and fins 63 is formed on an outer surface thereof.

Abstract: A method for manufacturing a wiring substrate includes alternately stacking first wiring patterns and first insulative layers on a first surface of a core substrate and alternately stacking second wiring patterns and second insulative layers on a second surface of the core substrate at an opposite side of the first surface. The number of the second insulative layers excluding the outermost second insulative layer differs from the number of the first insulative layers. The method further includes forming a via hole in the outermost first insulative layer to expose a portion of the outermost first wiring pattern, and exposing the outermost second wiring pattern by reducing the outermost second insulative layer in thickness. The method further includes forming a via in the via hole and forming a wiring pattern, which is connected by the via to the outermost first wiring pattern, on the outermost first insulative layer.

Abstract: In a semiconductor device manufacturing method, a semiconductor chip is mounted on a support board so as to expose a side of the semiconductor chip on which a plurality of terminal electrodes are provided. An insulating layer is formed so as to cover the side of the semiconductor chip on which the terminal electrodes are provided. Through electrodes connecting to the terminal electrodes and piercing the insulating layer are formed. Metal wirings connecting to the through electrodes are formed on the insulating layer. External terminal electrodes connecting the metal wiring are formed. Second spacing, spacing between the adjacent external terminal electrodes, is larger than first spacing, spacing between the adjacent terminal electrodes.

Abstract: A wiring board (package) has a structure in which multiple wiring layers are stacked one on top of another with insulating layers each interposed between corresponding two of the wiring layers, and the wiring layers are connected to one another through vias formed in each of the insulating layers. In a peripheral region of the package, reinforcing patterns are provided on the same surfaces where the corresponding wiring layers are provided, respectively. Each of the reinforcing patterns is formed of a conductive layer formed on the same surface where the corresponding one of the wiring layers is provided, and is provided in an intermittent ring-like shape when viewed in a planar view.

Abstract: A method for manufacturing a wiring substrate includes alternately stacking first wiring patterns and first insulative layers on a first surface of a core substrate and alternately stacking second wiring patterns and second insulative layers on a second surface of the core substrate at an opposite side of the first surface. The number of the second insulative layers excluding the outermost second insulative layer differs from the number of the first insulative layers. The method further includes forming a via hole in the outermost first insulative layer to expose a portion of the outermost first wiring pattern, and exposing the outermost second wiring pattern by reducing the outermost second insulative layer in thickness. The method further includes forming a via in the via hole and forming a wiring pattern, which is connected by the via to the outermost first wiring pattern, on the outermost first insulative layer.

Abstract: A wiring board has a wiring member, a first reinforcing member and a second reinforcing member. The wiring member has wiring layers and insulating layers which are stacked, and the wiring layers include a first connecting electrode formed on a surface of the wiring member and a second connecting electrode formed on a back surface of the wiring member. A pin is formed on the second connecting electrode. The second reinforcing member is formed by a resin and serves to reinforce the wiring member. The first reinforcing member is formed on the whole back surface of the wiring member except for the pin provided on the second connecting electrode.

Abstract: In a semiconductor device manufacturing method, a semiconductor chip is mounted on a support board so as to expose a side of the semiconductor chip on which a plurality of terminal electrodes are provided. An insulating layer is formed so as to cover the side of the semiconductor chip on which the terminal electrodes are provided. Through electrodes connecting to the terminal electrodes and piercing the insulating layer are formed. Metal wirings connecting to the through electrodes are formed on the insulating layer. External terminal electrodes connecting the metal wiring are formed. Second spacing, spacing between the adjacent external terminal electrodes, is larger than first spacing, spacing between the adjacent terminal electrodes.

Abstract: A wiring board 10 includes a wiring board main body 11 having a semiconductor device attaching pad 21 on which a semiconductor device 14 is attached, a dielectric layer 22 provided with the semiconductor device attaching pad 21, and a semiconductor device attaching area A in which the semiconductor device 14 is attached, and a stiffener bonded to a surface 22A of the dielectric layer 22 on the side where the semiconductor device attaching pad 21 is formed and having a semiconductor device attaching through portion 12A to expose the semiconductor device attaching area A, characterized in that a notch portion 41 for exposing the surface 22A of the dielectric layer 22 in a part located outside the semiconductor device attaching area A is provided on the outer periphery of the stiffener 12.

Abstract: A wiring board is provided. The wiring board includes: a resin substrate having a through-hole therethrough; metal foil patterns formed on the resin substrate; and a first wiring layer formed on the metal foil patterns and on an inner surface of the through-hole, wherein the first wiring layer includes: a first power feeding layer; and a first plated layer laminated on the first power feeding layer; a resin member filled in the through-hole and between adjacent wiring patterns of the first wiring layer, wherein an end surface of the resin member is flush with a surface of the first wiring layer; and a second wiring layer formed on the surface of the first wiring layer and formed to cover an end surface of the through-hole, wherein the second wiring layer includes: a second power feeding layer; and a second plated layer laminated on the second power feeding layer.

Abstract: In a method of manufacturing a wiring substrate of the present invention, a through-hole plating layer is formed from an inner surface of a through hole in a substrate to both surface sides, then a resin is filled in a through hole, and then a first resist in which an opening portion is provided on the through hole is formed. Then, a partial cover plating layer is formed in the opening portion in the first resist, then the first resist is removed, and then a second resist that covers a whole of the partial cover plating layer and has a pattern for patterning the through-hole plating layer is formed. Then, a pad wiring portion containing the partial cover plating layer and a wiring pattern are obtained by etching the through-hole plating layer while using the second resist as a mask.

Abstract: In a semiconductor device manufacturing method, a semiconductor chip is mounted on a support board so as to expose a side of the semiconductor chip on which a plurality of terminal electrodes are provided. An insulating layer is formed so as to cover the side of the semiconductor chip on which the terminal electrodes are provided. Through electrodes connecting to the terminal electrodes and piercing the insulating layer are formed. Metal wirings connecting to the through electrodes are formed on the insulating layer. External terminal electrodes connecting the metal wiring are formed. Second spacing, spacing between the adjacent external terminal electrodes, is larger than first spacing, spacing between the adjacent terminal electrodes.

Abstract: A wiring board (package) has a structure in which multiple wiring layers are stacked one on top of another with insulating layers each interposed between corresponding two of the wiring layers, and the wiring layers are connected to one another through vias formed in each of the insulating layers. In a peripheral region of the package, reinforcing patterns are provided on the same surfaces where the corresponding wiring layers are provided, respectively. Each of the reinforcing patterns is formed of a conductive layer formed on the same surface where the corresponding one of the wiring layers is provided, and is provided in an intermittent ring-like shape when viewed in a planar view.

Abstract: A semiconductor package includes a wiring substrate having a connection pad on both surface sides respectively, and a supporting plate provided on one surface side of the wiring substrate and formed of an insulator in which an opening portion is provided in a portion corresponding to the connection pad. The external connection terminals (the lead pins, or the like) are provided on the connection pads on the surface of the wiring substrate on which the supporting plate is provided, and the semiconductor chip is mounted on the connection pads on the opposite surface.

Abstract: A wiring board is provided. The wiring board includes: a resin substrate having a through-hole therethrough; metal foil patterns formed on the resin substrate; and a first wiring layer formed on the metal foil patterns and on an inner surface of the through-hole, wherein the first wiring layer includes: a first power feeding layer; and a first plated layer laminated on the first power feeding layer; a resin member filled in the through-hole and between adjacent wiring patterns of the first wiring layer, wherein an end surface of the resin member is flush with a surface of the first wiring layer; and a second wiring layer formed on the surface of the first wiring layer and formed to cover an end surface of the through-hole, wherein the second wiring layer includes: a second power feeding layer; and a second plated layer laminated on the second power feeding layer.

Abstract: A PGA type wiring board includes a wiring board to which a head portion of a pin is joined to a pad portion with solder interposed therebetween, and a pin fixing plate having a through hole formed therein through which a shank portion of the pin is inserted, and having an adhesive layer formed on one surface thereof. The pin fixing plate is bonded to the wiring board with the adhesive layer interposed therebetween while the shank portion of the pin is inserted through the through hole. The through hole is shaped in a stepped form with a two-step configuration when viewed in cross section.

Abstract: In a semiconductor device manufacturing method, a semiconductor chip is mounted on a support board so as to expose a side of the semiconductor chip on which a plurality of terminal electrodes are provided. An insulating layer is formed so as to cover the side of the semiconductor chip on which the terminal electrodes are provided. Through electrodes connecting to the terminal electrodes and piercing the insulating layer are formed. Metal wirings connecting to the through electrodes are formed on the insulating layer. External terminal electrodes connecting the metal wiring are formed. Second spacing, spacing between the adjacent external terminal electrodes, is larger than first spacing, spacing between the adjacent terminal electrodes.

Abstract: A wiring board 10 includes a wiring board main body 11 having a semiconductor device attaching pad 21 on which a semiconductor device 14 is attached, a dielectric layer 22 provided with the semiconductor device attaching pad 21, and a semiconductor device attaching area A in which the semiconductor device 14 is attached, and a stiffener bonded to a surface 22A of the dielectric layer 22 on the side where the semiconductor device attaching pad 21 is formed and having a semiconductor device attaching through portion 12A to expose the semiconductor device attaching area A, characterized in that a notch portion 41 for exposing the surface 22A of the dielectric layer 22 in a part located outside the semiconductor device attaching area A is provided on the outer periphery of the stiffener 12.

Abstract: A wiring board has a wiring member, a first reinforcing member and a second reinforcing member. The wiring member has wiring layers and insulating layers which are stacked, and the wiring layers include a first connecting electrode formed on a surface of the wiring member and a second connecting electrode formed on a back surface of the wiring member. A pin is formed on the second connecting electrode. The second reinforcing member is formed by a resin and serves to reinforce the wiring member. The first reinforcing member is formed on the whole back surface of the wiring member except for the pin provided on the second connecting electrode.

Abstract: In a method of manufacturing a wiring substrate of the present invention, a through-hole plating layer is formed from an inner surface of a through hole in a substrate to both surface sides, then a resin is filled in a through hole, and then a first resist in which an opening portion is provided on the through hole is formed. Then, a partial cover plating layer is formed in the opening portion in the first resist, then the first resist is removed, and then a second resist that covers a whole of the partial cover plating layer and has a pattern for patterning the through-hole plating layer is formed. Then, a pad wiring portion containing the partial cover plating layer and a wiring pattern are obtained by etching the through-hole plating layer while using the second resist as a mask.