Abstract: In a process of fabricating a MISFET of the LDD structure, a gate insulation film is formed on a semiconductor substrate or a semiconductor thin film. A gate electrode is formed on the gate insulation film, and lightly-doped regions are formed in the semiconductor substrate or the semiconductor thin film by ion implantation using the gate electrode as a mask. Next, a CVD oxide film containing an impurity is unselectively deposited, sidewalls are formed along the edges of the gate electrodes by anisotropic etching, and heavily-doped source and drain regions are formed in the semiconductor substrate or the semiconductor thin film by ion implanation using the gate electrode and the sidewalls as a mask.

Abstract: An LDD MIS FET comprises a silicide over the lightly doped regions to reduce the parasitic resistance and to prevent the depletion of the lightly-doped regions, reducing the hot carrier injection effect. By the provision of the silicide, the overall parasitic resistance can be made low. Moreover, the increase in the resistance of the lightly-doped region due to the negative charge being trapped at the interface of or in the oxide film over the lighty-doped region and the resultant degradation in the characteristic are eliminated.

Abstract: The semiconductor memory element comprises two capacitors and a switching MOS transistor. A first capacitor is constituted by a silicon semiconductor substrate, a thin oxide film and a first doped polycrystalline silicon layer, and a second capacitor is constituted by a second doped polycrystalline silicon layer, a thin oxide film between the first and the second doped polycrystalline silicon layers, and the first polycrystalline silicon layer. Interconnection layers necessary to form a single transistor type dynamic memory cell are also provided.

Abstract: A method of making semiconductor devices having fine dielectric element isolation regions is disclosed. The method comprises the steps of preparing a semiconductor substrate of one conductivity type which is in a high impurity concentration; forming on the surface of the semi-conductor substrate an epitaxial layer having the same conductivity type as that of the semiconductor substrate in a low impurity concentration; etching off selected regions of the epitaxial layer so as to form islands of the epitaxial layer; forming a CVD oxide layer all over the surface of the structure obtained by the steps; applying high-molecular material film all over the surface of the oxide layer; and removing both the oxide layer and the high-molecular material film so as to expose the surface of the islands, whereby fine element isolation regions of the oxide layer are obtained between the islands.