Patents by Inventor Akiomi Hiruma

Akiomi Hiruma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100001048
    Abstract: A soldering method for soldering an electronic part on a substrate by reflow soldering is disclosed that includes the steps of applying a solder paste on the substrate; mounting the electronic part on the substrate by using the solder paste; disposing a heat capacity enhancing member on the electronic part, the heat capacity enhancing member including a gel-like material able to enhance the heat capacity of the electronic part; and soldering the electronic part onto the substrate by reflow soldering with the heat capacity enhancing member being applied thereon.
    Type: Application
    Filed: September 11, 2009
    Publication date: January 7, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Tsuyoshi Yamamoto, Akiomi Hiruma, Fumigi Koyama
  • Publication number: 20060266806
    Abstract: A soldering method for soldering an electronic part on a substrate by reflow soldering is disclosed that includes the steps of applying a solder paste on the substrate; mounting the electronic part on the substrate by using the solder paste; disposing a heat capacity enhancing member on the electronic part, the heat capacity enhancing member including a gel-like material able to enhance the heat capacity of the electronic part; and soldering the electronic part onto the substrate by reflow soldering with the heat capacity enhancing member being applied thereon.
    Type: Application
    Filed: August 23, 2005
    Publication date: November 30, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Tsuyoshi Yamamoto, Akiomi Hiruma, Fumigi Koyama
  • Patent number: 6664625
    Abstract: A semiconductor device comprises a substrate, a mounting chip, multi-stage bumps, and a sheet-like interposer member. The mounting chip is bonded to the substrate. The multi-stage bumps have two or more stages of bumps stacked and bonded so that the substrate and the mounting chip are electrically connected by the multi-stage bumps. The interposer member is of a resin material and provided in the stacked stages of the multi-stage bumps. The interposer member has openings each formed between two diagonally arrayed bumps of the multi-stage bumps.
    Type: Grant
    Filed: October 17, 2002
    Date of Patent: December 16, 2003
    Assignee: Fujitsu Limited
    Inventor: Akiomi Hiruma
  • Publication number: 20030168728
    Abstract: A semiconductor device comprises a substrate, a mounting chip, multi-stage bumps, and a sheet-like interposer member. The mounting chip is bonded to the substrate. The multi-stage bumps have two or more stages of bumps stacked and bonded so that the substrate and the mounting chip are electrically connected by the multi-stage bumps. The interposer member is of a resin material and provided in the stacked stages of the multi-stage bumps. The interposer member has openings each formed between two diagonally arrayed bumps of the multi-stage bumps.
    Type: Application
    Filed: October 17, 2002
    Publication date: September 11, 2003
    Applicant: FUJITSU LIMITED
    Inventor: Akiomi Hiruma