Abstract: A first gate drive outputs a first drive voltage to turn a first transistor on upon occurrence of a condition in which a voltage at a supply terminal is higher than a voltage at a ground terminal, the output first drive voltage being higher than the voltage at the ground terminal. A second gate drive outputs a second drive voltage to turn a second transistor on, upon occurrence of a condition in which the voltage at the supply terminal is lower than the voltage at the ground terminal, the output second drive voltage being higher than the voltage at the supply terminal.

Abstract: In a sine-wave multiplier, signal components included in an output signal Qu1 and corresponding to the product of a third-order harmonic component of a first square wave W1 and an input signal Vi and the product of a fifth-order harmonic component of the first square wave W1 and the input signal Vi are offset by a signal component included in an output signal Qu2 and corresponding to the product of a fundamental component of a second square wave W2 and the input signal Vi and a signal component included in an output signal Qu3 and corresponding to the product of a fundamental component of a second square wave W3 and the input signal Vi.

Abstract: In a sine-wave multiplier, signal components included in an output signal Qu1 and corresponding to the product of a third-order harmonic component of a first square wave W1 and an input signal Vi and the product of a fifth-order harmonic component of the first square wave W1 and the input signal Vi are offset by a signal component included in an output signal Qu2 and corresponding to the product of a fundamental component of a second square wave W2 and the input signal Vi and a signal component included in an output signal Qu3 and corresponding to the product of a fundamental component of a second square wave W3 and the input signal Vi.

Abstract: A differential signal is input to a pair of gates of a differential pair, a differential signal generated by a load circuit connected to drains of the differential pair is amplified by a differential amplifier stage, and the amplified differential signal is fed back to a pair of sources of the differential pair via a feedback circuit. It is possible to maintain a high input impedance in the pair of gates of the differential pair while not being influenced by a gain of negative feedback of an amplifier circuit, and it is possible to perform amplification in an input stage by using a pair of a first transistor and a second transistor of the differential pair. Therefore, compared with the related art, it is possible to decrease the number of transistors in the input stage and to reduce a flicker noise.

Abstract: In a reset period of a first stage, a switching circuit is turned on, and high-level driving voltages are output from driving circuits. In a charge transfer period subsequent to the reset period, the switching circuit is turned off, and low-level driving voltages are output from the driving circuits. It is determined whether or not an output voltage of an amplifier circuit in the charge transfer period is included in a normal range. In the inspection of a second stage subsequent to the first stage, in the same manner as in the normal measurement, voltages having opposite phases are output from the driving circuits in the reset period and the charge transfer period, and it is determined whether or not the output voltage of the amplifier circuit in the charge transfer period is included in a normal range.

Abstract: A first transistor and a second transistor form a current mirror circuit. A second current flowing in the second transistor is kept constant by a current control circuit. Therefore, a first current, to be output to a load, in the first transistor is kept at a constant value responsive to the second current in the second transistor. Since a drain voltage in the second transistor is controlled so as to become equal to a drain voltage in the first transistor, even if a voltage at an output terminal changes in response to a change in the impedance of the load, a ratio between the first current and the second current becomes substantially equal to a size ratio K between the first transistor and the second transistor. That is, the first current and second current precisely operate as a current mirror circuit.

Abstract: A differential signal is input to a pair of gates of a differential pair, a differential signal generated by a load circuit connected to drains of the differential pair is amplified by a differential amplifier stage, and the amplified differential signal is fed back to a pair of sources of the differential pair via a feedback circuit. It is possible to maintain a high input impedance in the pair of gates of the differential pair while not being influenced by a gain of negative feedback of an amplifier circuit, and it is possible to perform amplification in an input stage by using a pair of a first transistor and a second transistor of the differential pair. Therefore, compared with the related art, it is possible to decrease the number of transistors in the input stage and to reduce a flicker noise.

Abstract: The highest voltage of a power supply voltage, a ground potential, and a signal voltage is output as a selection voltage from a terminal on the output side. In this case, terminals on the input side and the terminal on the output side are connected to each other through MOS transistors in the ON state. Therefore, it is possible to suppress a voltage drop due to a parasitic diode of each MOS transistor.

Abstract: The highest voltage of a power supply voltage, a ground potential, and a signal voltage is output as a selection voltage from a terminal on the output side. In this case, terminals on the input side and the terminal on the output side are connected to each other through MOS transistors in the ON state. Therefore, it is possible to suppress a voltage drop due to a parasitic diode of each MOS transistor.

Abstract: In a reset period of a first stage, a switching circuit is turned on, and high-level driving voltages are output from driving circuits. In a charge transfer period subsequent to the reset period, the switching circuit is turned off, and low-level driving voltages are output from the driving circuits. It is determined whether or not an output voltage of an amplifier circuit in the charge transfer period is included in a normal range. In the inspection of a second stage subsequent to the first stage, in the same manner as in the normal measurement, voltages having opposite phases are output from the driving circuits in the reset period and the charge transfer period, and it is determined whether or not the output voltage of the amplifier circuit in the charge transfer period is included in a normal range.

Abstract: A protection circuit includes a power supply terminal, a ground terminal, a control unit connected to the power supply terminal and the ground terminal, and a supply unit connected to the power supply terminal and the ground terminal, for preventing application of voltage in a reverse direction to a circuit unit having a predetermined function. In this case, the control unit generates a control potential, which controls the control unit and the supply unit in accordance with a potential supplied from the power supply terminal and a potential supplied from the ground terminal. The supply unit is configured to be capable of supplying current to a circuit unit connected to a subsequent stage on the basis of a potential supplied from the power supply terminal, a potential supplied from the ground terminal, and the control potential generated by the control unit.

Abstract: A protection circuit includes a power supply terminal, a ground terminal, a control unit connected to the power supply terminal and the ground terminal, and a supply unit connected to the power supply terminal and the ground terminal, for preventing application of voltage in a reverse direction to a circuit unit having a predetermined function. In this case, the control unit generates a control potential, which controls the control unit and the supply unit in accordance with a potential supplied from the power supply terminal and a potential supplied from the ground terminal. The supply unit is configured to be capable of supplying current to a circuit unit connected to a subsequent stage on the basis of a potential supplied from the power supply terminal, a potential supplied from the ground terminal, and the control potential generated by the control unit.

Abstract: A balanced gain control amplifier contains first and second transistors differentially connected to each other and having their emitters connected to a first current source. The balanced gain control amplifier also contains third and fourth transistors differentially connected to each other and having their emitters connected to a second constant current source. The collectors of the first and fourth transistors are connected to a power terminal through a common first load resistor, and the collectors of the second and third transistors are connected to the power terminal through a common second load resistor. A signal may be input between the bases of the first and third transistors and the bases of the second and fourth transistors. The current of the second constant current source is variable in a range no more than the current value of the first constant current source.

Abstract: A balanced gain control amplifier contains first and second transistors differentially connected to each other and having their emitters connected to a first current source. The balanced gain control amplifier also contains third and fourth transistors differentially connected to each other and having their emitters connected to a second constant current source. The collectors of the first and fourth transistors are connected to a power terminal through a common first load resistor, and the collectors of the second and third transistors are connected to the power terminal through a common second load resistor. A signal may be input between the bases of the first and third transistors and the bases of the second and fourth transistors. The current of the second constant current source is variable in a range no more than the current value of the first constant current source.