Abstract: Some embodiments use a machine-trained network during routing to provide the router with sufficient information to improve the quality of routes generated by a router. This machine-trained network in some embodiments is referred to as the “digital twin” of a lengthy design and/or manufacturing process that produces the design of an IC layout and/or manufactures an IC based on a designed IC layout. The digital twin in some embodiments provides information regarding parasitics, regarding redundant vias for insertion or regarding complexity of subsequent manufacturing processes used to manufacture an IC based on the IC design layout.

Abstract: Methods for fracturing a pattern to be exposed on a surface using variable shaped beam (VSB) lithography include inputting an initial pattern; calculating a first substrate pattern from the initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by a union of the initial pattern with locations on the grid; and merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots. The method also includes calculating a calculated pattern to be exposed on the surface with the modified set of VSB shots; and calculating a second substrate pattern from the calculated pattern to be exposed on the surface.

Abstract: Methods and systems for reticle enhancement technology (RET) include inputting a target wafer pattern, where the target wafer pattern spans an entire design area. The entire design area is divided into a plurality of tiles, each tile having a halo region surrounding the tile. An optimized mask is calculated, wherein the optimized mask is generated by a first trained neural network using the target wafer patter. The calculating is performed for each tile in the plurality of tiles including its halo region.

Abstract: Provided is an efficient method for attaching a tissue section. In the invention, one of problems is solved by changing attachment conditions of the tissue section depending on an organ from which the tissue section is derived. A technique of achieving good adhesiveness between a microscope slide and a section by introducing unevenness on a front surface of the microscope slide using reactive ion etching as one of the attachment conditions is provided. Further, a technique of optimizing the attachment of the section using a machine learning technique or the like is provided.

Abstract: Methods incorporate variable side wall angle (VSA) into calculated patterns, using a mask 3D (M3D) effect. Embodiments include inputting a mask exposure information, calculating a mask 2D (M2D) effect from the mask exposure information, and determining the M3D effect from the M2D effect. Determining the M3D effect may include determining the VSA, such as by using a neural network. Embodiments may include determining a dose margin from mask exposure information; calculating a VSA using the dose margin; and calculating a pattern on a substrate using the calculated VSA, wherein calculating the pattern on the substrate includes a mask 3D effect.

Abstract: A method for exposing a pattern in an area on a surface using a charged particle beam lithography is disclosed and includes inputting an original set of exposure information for the area. The area comprises a plurality of pixels, and the original set of exposure information comprises dosages for the plurality of pixels in the area. A backscatter is calculated for a sub area of the area based on the original set of exposure information including the dosages for the plurality of pixels in the area. An increase in dosage for at least one pixel in a plurality of pixels in the sub area is determined, in a location where the backscatter of the sub area is below a pre-determined threshold, thereby increasing the backscatter of the sub area.

Abstract: Some embodiments use a machine-trained network during routing to provide the router with sufficient information to improve the quality of routes generated by a router. This machine-trained network in some embodiments is referred to as the “digital twin” of a lengthy design and/or manufacturing process that produces the design of an IC layout and/or manufactures an IC based on a designed IC layout. The digital twin in some embodiments provides information regarding parasitics, regarding redundant vias for insertion or regarding complexity of subsequent manufacturing processes used to manufacture an IC based on the IC design layout.

Abstract: Some embodiments use a machine-trained network during routing to provide the router with sufficient information to improve the quality of routes generated by a router. This machine-trained network in some embodiments is referred to as the “digital twin” of a lengthy design and/or manufacturing process that produces the design of an IC layout and/or manufactures an IC based on a designed IC layout. The digital twin in some embodiments provides information regarding parasitics, regarding redundant vias for insertion or regarding complexity of subsequent manufacturing processes used to manufacture an IC based on the IC design layout.

Abstract: Methods and systems for exposing a desired shape in an area on a surface using a charged particle beam system include determining a local pattern density for the area, based on an original set of exposure information. A pre-proximity effect correction (PEC) maximum dose for the local pattern density is determined, based on a pre-determined target post-PEC maximum dose. The pre-PEC maximum dose may be calculated near an edge of the desired shape. Methods also include modifying the original set of exposure information with the pre-PEC maximum dose to create a modified set of exposure information.

Abstract: Some embodiments use a machine-trained network during routing to provide the router with sufficient information to improve the quality of routes generated by a router. This machine-trained network in some embodiments is referred to as the “digital twin” of a lengthy design and/or manufacturing process that produces the design of an IC layout and/or manufactures an IC based on a designed IC layout. The digital twin in some embodiments provides information regarding parasitics, regarding redundant vias for insertion or regarding complexity of subsequent manufacturing processes used to manufacture an IC based on the IC design layout.

Abstract: Some embodiments use a machine-trained network during routing to provide the router with sufficient information to improve the quality of routes generated by a router. This machine-trained network in some embodiments is referred to as the “digital twin” of a lengthy design and/or manufacturing process that produces the design of an IC layout and/or manufactures an IC based on a designed IC layout. The digital twin in some embodiments provides information regarding parasitics, regarding redundant vias for insertion or regarding complexity of subsequent manufacturing processes used to manufacture an IC based on the IC design layout.

Abstract: Some embodiments use a machine-trained network during routing to provide the router with sufficient information to improve the quality of routes generated by a router. This machine-trained network in some embodiments is referred to as the “digital twin” of a lengthy design and/or manufacturing process that produces the design of an IC layout and/or manufactures an IC based on a designed IC layout. The digital twin in some embodiments provides information regarding parasitics, regarding redundant vias for insertion or regarding complexity of subsequent manufacturing processes used to manufacture an IC based on the IC design layout.

Abstract: Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include inputting a desired pattern to be formed on a substrate; determining an initial mask pattern from the desired pattern for the substrate; optimizing the initial mask pattern for wafer quality using a VSB exposure system; and outputting the optimized mask pattern. Methods for fracturing a pattern to be exposed on a surface using VSB lithography include inputting an initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by the union of the initial pattern with locations on the grid; merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots.

Abstract: Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

Abstract: Methods for reticle enhancement technology (RET) for use with variable shaped beam (VSB) lithography include determining an initial mask pattern from a desired pattern for a substrate; calculating a first substrate pattern from the initial mask pattern; determining an initial set of VSB shots that will form the initial mask pattern; calculating a simulated mask pattern from the initial set of VSB shots; calculating a second substrate pattern from the simulated mask pattern; and adjusting the initial set of VSB shots, wherein the adjusting of the initial set of VSB shots creates an adjusted set of VSB shots.

Abstract: Methods for fracturing a pattern to be exposed on a surface using variable shaped beam (VSB) lithography include inputting an initial pattern; calculating a first substrate pattern from the initial pattern; overlaying the initial pattern with a two-dimensional grid, wherein an initial set of VSB shots are formed by a union of the initial pattern with locations on the grid; and merging two or more adjacent shots in the initial set of VSB shots to create a larger shot in a modified set of VSB shots; and outputting the modified set of VSB shots. The method also includes calculating a calculated pattern to be exposed on the surface with the modified set of VSB shots; and calculating a second substrate pattern from the calculated pattern to be exposed on the surface.

Abstract: Methods for exposing a desired shape in an area on a surface using a charged particle beam system include determining a local pattern density for the area of the desired shape based on an original set of exposure information. A backscatter for a sub area is calculated, based on the original set of exposure information. Dosage for at least one pixel in a plurality of pixels in the sub area is increased, in a location where the backscatter of the sub area is below a pre-determined threshold, thereby increasing the backscatter of the sub area. A pre-PEC maximum dose is determined for the local pattern density, based on a pre-determined target post-PEC maximum dose. The original set of exposure information is modified with the pre-PEC maximum dose and the increased dosage of the at least one pixel in the sub area to create a modified set of exposure information.

Abstract: Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

Abstract: Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.

Abstract: Some embodiments of the invention provide an integrated circuit (IC) that has a novel non-preferred direction (NPD) wiring architecture. In some embodiments, the IC includes a substrate and multiple wiring layers, which include a first set of one or more wiring layers with no preferred wiring directions, and a second set of one or more wiring layers with preferred wiring directions. In some embodiments, the first set of wiring layers includes the third and fourth wiring layers, while the second set of wiring layers includes the fifth and higher metal layers with successive neighboring layers having different (e.g., alternating) preferred wiring directions. The first set of wiring layers in other embodiments includes the third wiring layer but not the fourth wiring layer, which in these embodiments has a preferred wiring direction.