Abstract: Memories might include a controller configured to cause the memory to apply a first voltage level indicative of a data state of a memory cell of an array of memory cells to a control gate of a transistor, retain the first voltage level on the control gate of the transistor, connect a first source/drain of the transistor to a data line corresponding to the memory cell while applying a second voltage level to a second source/drain of the transistor and while retaining the first voltage level on the control gate of the transistor, and apply a programming pulse to a control gate of the memory cell while the data line is connected to the first source/drain of the transistor.

Abstract: Methods, apparatuses and systems related to maintaining stored data are described. The apparatus may be configured to refresh the stored data according to schedule that includes different delays between successive refresh operations.

Abstract: A method includes determining a logical saturation of a memory device in a memory sub-system and adjusting a code rate of the memory device based on the logical saturation, wherein the code rate represents a ratio of user data to a combination of the user data and error correction data.

Abstract: A transistor comprises a lower contact structure, a channel structure, a dielectric fill structure, and an upper contact structure. The lower contact structure comprises a first oxide semiconductive material. The channel structure contacts the lower contact structure and comprises a second oxide semiconductive material having a smaller atomic concentration of one or more metals than the first oxide semiconductive material. The dielectric fill structure contacts an inner side surface of the channel structure and has a recessed upper surface relative to the channel structure. The upper contact structure comprises a third oxide semiconductive material having a greater atomic concentration of the one or more metals than the channel structure. The upper contact structure comprises a first portion contacting the upper surface of the dielectric fill structure and the inner side surface of the channel structure, and a second portion contacting the upper surface of the channel structure.

Abstract: A system related to providing multi-layer code rates for special event protection with reduced performance penalty for memories is disclosed. Based on an impending stress event, extra error correction code data is utilized to encode user data obtained from a host. The user data and first error correction code data are written to a first block and the extra error correction code data is written to a second block. Upon stress event completion, pages having user data with the extra error correction code data are scanned. If pages of the first block are unable to satisfy reliability requirements, a touch-up process is executed on each page in the first block to reinstate the first block so that the extra error correction code data is no longer needed. The extra error correction code data is deleted from the second block and the second block is made available for user data.

Abstract: An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.

Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first and second block and a first and second user data portion are directed to the first and second block. Temporary parity data is generated using the first and second user data portions. The temporary parity data and the first and second user data portions are stored in a buffer. Portions of the first and second block are programmed with two programming passes. The first and second user data portions in the buffer are invalidated in response to a completion of the second programming pass of the portions of the first and second blocks. The temporary parity data is maintained in the buffer until a second programming pass of the first and second block.

Abstract: A memory device includes a memory array including wordlines and at least one string of cells. Each cell of the at least one string of cells is addressable by a respective wordline. The memory device further includes control logic, operatively coupled to the memory array, to perform operations including generating gate-induced drain leakage (GIDL) with respect to the at least one string of cells, and causing a grounding voltage to be applied to a set of wordlines to ground each cell of the at least one string of cells addressable by each wordline of the set of wordlines. The grounding voltage applied to the set of wordlines enables transport of positive charge carriers generated by the GIDL. In some embodiments, the positive charge carriers neutralize a buildup of negative charge carriers generated during a seeding phase of a program refresh operation.

Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first block and a second block. A buffer is allocated for executing the write command to the first block. The buffer includes multiple buffer decks and the buffer holds the user data written to the first block. User data is programmed into the first block to a threshold percentage. The threshold percentage is less than one hundred percent of the first block. A buffer deck is invalidated in response to programming the first block to the threshold percentage. The buffer deck is reallocated to the second block for programming the user data into the second block. The buffer deck holds user data written to the second block.

Abstract: Methods, systems, and apparatuses include retrieving a defectivity footprint of a portion of memory, the portion of memory composed of multiple blocks. A deck programming order is determined, based on the defectivity footprint, for a current block of the multiple blocks. The current block is composed of multiple decks. The deck programming order is an order in which the multiple decks are programmed. The multiple decks programmed according to the determined deck programming order.

Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.

Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.

Abstract: A system can include a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving data to be stored on the memory device, storing a first copy of the data in a first set of memory cells of the memory device, and storing a second copy of the data in a second set of memory cells of the memory device. The operations can also include reading the first copy of the data and determining whether a threshold voltage of a cell in the first set of memory cells is within an overlapping range of voltage distributions, and reading the second copy of the data and determining whether the threshold voltage of a cell in the second set of memory cells is within an overlapping range of voltage distributions. They can also include using the second copy of the data.

Abstract: A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The first read command is with respect to a set of memory cells of the memory device. The processing device is further to receive a second read command at a second time. The second read command is with respect to the set of memory cells of the memory device. The processing device is further to increment a read counter for the memory device by a value reflecting a difference between the first time and the second time. The processing device is further to determine that a value of the read counter satisfies a threshold criterion. The processing device is further to perform a data integrity scan with respect to the set of memory cells.

Abstract: A method includes receiving first data, determining a number of programming operations performed on a plurality of flash memory cells subsequent to a most recent erase operation performed on the plurality of flash memory cells, encoding the first data to provide a first write-once memory (WOM) encoded data, and storing the first WOM encoded data, based at least in part on the determined number of programming operations, within a number of the plurality of flash memory cells.

Abstract: A method includes causing a first set of memory cells, associated with a first wordline of a memory array, to be programmed with a first set of threshold voltage distributions; causing a second set of memory cells, associated with a second wordline adjacent to the first wordline, to be programmed with a second set of threshold voltage distributions; after programming the second set of cells, causing the first set of memory cells to be coarse programmed with an intermediate third set of threshold voltage distributions that is at least twice in number compared to the first set; and causing the first set of memory cells to be fine programmed with a final third set of threshold voltage distributions. At least some threshold voltage distributions of the final third set of threshold voltage distributions have wider read window margins than those of the intermediate third set of threshold voltage distributions.

Abstract: A microelectronic device comprises a memory array region, a control logic region, and an additional control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures, and vertically extending strings of memory cells within the stack structure. The control logic region underlies the stack structure and comprises control logic devices configured to effectuate a portion of control operations for the vertically extending strings of memory cells. The additional control logic region overlies the stack structure and comprises additional control logic devices configured to effectuate an additional portion of the control operations for the vertically extending strings of memory cells. Methods of forming a microelectronic device, and additional microelectronic devices and electronic systems are also described.

Abstract: A read is initiated with respect to a target cell. A pair of adjacent cells includes a first cell and a second cell each adjacent to the target cell. First cell state information is obtained for the first cell and second cell state information is obtained for the second cell. A state information bin is determined by applying a pre-defined operation to the first cell state information and the second cell state information of the respective pair of adjacent cells. The target cell is assigned to the state information bin. Each state information bin defines a read level offset for reading the target cell.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers located one over another, each of the tiers including memory cells and a control gate for the memory cells, each of the tiers including first transistors connected in series between the control gate in a respective tier and a conductive line, and second transistors connected in series between the control gate in the respective tier and the conductive line, the second transistors connected in parallel with the first transistors between the control gate and the conductive line, conductive joints coupled to channel regions of the first and second transistors, and gates for the first transistors and second transistors, each of the gates shared by one of the first transistors and one of the second transistors.

Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.