Patents by Inventor Akira Hirao
Akira Hirao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136936Abstract: Provided are a positive electrode terminal and a negative electrode terminal being terminals of a capacitor element; a positive electrode conductor plate connected to the positive electrode terminal; a negative electrode conductor plate connected to the negative electrode terminal; and a power conversion module connected to the two conductor plates. The positive electrode terminal and the negative electrode terminal are formed along an arrangement direction of the capacitor element. The positive electrode conductor plate and the negative electrode conductor plate form a laminated conductor portion in which the positive electrode conductor plate and the negative electrode conductor plate have respective main surfaces disposed, to face the main surface of the capacitor element, and are laminated to each other.Type: ApplicationFiled: September 29, 2021Publication date: April 25, 2024Inventors: Akira MIMA, Takeshi TOKUYAMA, Junpei KUSUKAWA, Takashi HIRAO
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Patent number: 11964462Abstract: The present invention provides an electrical debonding type adhesive sheet capable of producing a joined body in which a voltage can be stably applied to an electrical debonding type adhesive layer. An electrical debonding type adhesive sheet according to a first embodiment of the present invention includes a first adhesive layer, a substrate for voltage application including an electroconductive layer and a base layer, and a second adhesive layer in this order, and has a first protrudent part, in which the first adhesive layer and the substrate for voltage application extend and protrude with respect to the second adhesive layer, and a second protrudent part, in which the substrate for voltage application extends from the first protrudent part and protrudes with respect to the first adhesive layer.Type: GrantFiled: March 6, 2023Date of Patent: April 23, 2024Assignee: NITTO DENKO CORPORATIONInventors: Kaori Akamatsu, Kaori Mizobata, Ryo Awane, Akira Hirao, Junji Yokoyama, Yosuke Shimizu
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Publication number: 20240128241Abstract: A semiconductor device includes: an insulated circuit substrate including a conductive plate on a top surface side; a semiconductor chip mounted on the conductive plate; and an external connection terminal electrically connected to the semiconductor chip and including an inner-side conductor layer, an outer-side conductor layer provided at a circumference of the inner-side conductor layer, and an insulating layer interposed between the inner-side conductor layer and the outer-side conductor layer.Type: ApplicationFiled: August 23, 2023Publication date: April 18, 2024Applicant: FUJI ELECTRIC CO., LTD.Inventors: Akira HIRAO, Yoshinari IKEDA, Motohito HORI
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Patent number: 11956933Abstract: No consideration is given to heat transferred from a semiconductor module to a capacitor via a bus bar module. The heat generated by a semiconductor module (1) is transferred to a bus bar module (3) via a DC terminal (1A) of the semiconductor module (1). As illustrated in FIG. 4(B), the heat transferred to the bus bar module 3 is then transferred to the pressing member 5 via the annular conductor 8 and the bolt 5A. Since the pressing member 5 is in close contact with the second cooler 2B, the heat transferred to the pressing member 5 is cooled by the second cooler 2B. On the other hand, the heat transferred to the convex portion 6A of the housing 6 is transferred to the first cooler 2A via the housing 6 and cooled. As a result, in the configuration in which a capacitor (4) is connected to the semiconductor module (1) via the bus bar module (3), the heat transferred from the semiconductor module (1) to the capacitor (4) can be suppressed.Type: GrantFiled: July 31, 2020Date of Patent: April 9, 2024Assignee: Hitachi Astemo, Ltd.Inventors: Takashi Hirao, Takeshi Tokuyama, Noriyuki Maekawa, Akira Matsushita, Toshiya Satoh
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Publication number: 20240006287Abstract: A semiconductor device includes an insulated circuit substrate, a semiconductor chip, a printed circuit board, an interposer, and a sealing member, the interposer including a plurality of post electrodes each having one end bonded to the semiconductor chip via a solder layer, an insulating layer provided to be separately opposed to the semiconductor chip and provided with a first penetration hole filled with part of the solder layer, and a conductor layer provided to be opposed to the printed circuit board and connected to another end of each of the post electrodes via the insulating layer.Type: ApplicationFiled: April 25, 2023Publication date: January 4, 2024Applicant: FUJI ELECTRIC CO., LTD.Inventors: Motohito HORI, Yoshinari IKEDA, Akira HIRAO
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Publication number: 20230411313Abstract: A semiconductor device includes: an insulated circuit substrate; a semiconductor chip provided on the insulated circuit substrate; a first external connection terminal provided on the insulated circuit substrate; a relay terminal provided on the insulated circuit substrate; a printed circuit board arranged over the semiconductor chip and connected to the first external connection terminal and the relay terminal; and a first snubber circuit provided on the printed circuit board and having one end connected to the first external connection terminal via the printed circuit board and another end connected to the relay terminal via the printed circuit board.Type: ApplicationFiled: April 24, 2023Publication date: December 21, 2023Applicant: FUJI ELECTRIC CO., LTD.Inventors: Akira HIRAO, Yoshinari IKEDA, Motohito HORI
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Publication number: 20230256710Abstract: The present invention provides an electrical debonding type adhesive sheet capable of producing a joined body in which a voltage can be stably applied to an electrical debonding type adhesive layer. An electrical debonding type adhesive sheet according to a first embodiment of the present invention includes a first adhesive layer, a substrate for voltage application including an electroconductive layer and a base layer, and a second adhesive layer in this order, and has a first protrudent part, in which the first adhesive layer and the substrate for voltage application extend and protrude with respect to the second adhesive layer, and a second protrudent part, in which the substrate for voltage application extends from the first protrudent part and protrudes with respect to the first adhesive layer.Type: ApplicationFiled: March 6, 2023Publication date: August 17, 2023Inventors: Kaori AKAMATSU, Kaori MIZOBATA, Ryo AWANE, Akira HIRAO, Junji YOKOYAMA, Yosuke SHIMIZU
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Publication number: 20230260859Abstract: A semiconductor device includes a semiconductor module that includes: an insulating circuit board, a semiconductor chip provided on a main surface of the insulating circuit board, and an external connection terminals provided on the main surface of the insulating circuit board; an external printed circuit board provided so as to face a main surface of the semiconductor module, the external printed circuit board having a through hole into which the external connection terminal is inserted; and an elastic member provided between the main surface of the semiconductor module and the external printed circuit board so as to apply a pressing force to the main surface of the semiconductor module.Type: ApplicationFiled: January 3, 2023Publication date: August 17, 2023Applicant: Fuji Electric Co., Ltd.Inventors: Motohito HORI, Yoshinari IKEDA, Akira HIRAO
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Patent number: 11658231Abstract: A semiconductor device having a semiconductor module. The semiconductor module includes first and second conductor layers facing each other, a first semiconductor element provided between the first and second conductor layers, positive and negative electrode terminals respectively provided on edge portions of the first and second conductor layers at a first side of the semiconductor module in a top view of the semiconductor module, control wiring that is electrically connected to the first control electrode, and that extends out of the first and second conductor layers at a second side of the semiconductor module that is opposite to the first side in the top view, and a control terminal that is electrically connected to the control wiring, that is positioned outside the first and second conductor layers in the top view, and that has an end portion that is aligned with the positive and negative electrode terminals.Type: GrantFiled: October 30, 2020Date of Patent: May 23, 2023Assignee: FUJI ELECTRIC CO., LTD.Inventors: Motohito Hori, Yoshinari Ikeda, Akira Hirao, Tsunehiro Nakajima
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Patent number: 11623429Abstract: The present invention provides an electrical debonding type adhesive sheet capable of producing a joined body in which a voltage can be stably applied to an electrical debonding type adhesive layer. An electrical debonding type adhesive sheet according to a first embodiment of the present invention includes a first adhesive layer, a substrate for voltage application including an electroconductive layer and a base layer, and a second adhesive layer in this order, and has a first protrudent part, in which the first adhesive layer and the substrate for voltage application extend and protrude with respect to the second adhesive layer, and a second protrudent part, in which the substrate for voltage application extends from the first protrudent part and protrudes with respect to the first adhesive layer.Type: GrantFiled: March 6, 2019Date of Patent: April 11, 2023Assignee: NITTO DENKO CORPORATIONInventors: Kaori Akamatsu, Kaori Mizobata, Ryo Awane, Akira Hirao, Junji Yokoyama, Yosuke Shimizu
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Patent number: 11605582Abstract: A semiconductor device includes a wiring board that includes a first insulating layer, a first conductive layer arranged over the first insulating layer, a second conductive layer arranged under the first insulating layer, the wiring board further including a magnetic layer that is arranged between the first insulating layer and the first or second conductive layer and that has a higher specific magnetic permeability than the first and second conductive layers, and a carbon layer that is arranged between the first insulating layer and the first or second conductive layer and that has a higher thermal conductivity in a planary direction than the first and second conductive layers; a semiconductor chip electrically connected to the first and second conductive layers; and an insulating circuit board arranged separately from the wiring board and that has the semiconductor chip mounted thereon.Type: GrantFiled: August 2, 2021Date of Patent: March 14, 2023Assignee: FUJI ELECTRIC CO., LTD.Inventors: Takahiro Mitsumoto, Akira Hirao, Motohito Hori
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Publication number: 20220406689Abstract: A semiconductor device includes: an insulated circuit substrate including a conductive plate on a top surface side; a semiconductor chip mounted on the conductive plate; a printed circuit board provided over and electrically connected to the semiconductor chip; a first external connection terminal electrically connected to the conductive plate and extending upward from the conductive plate; a first conductive block provided to surround an outer circumference of the first external connection terminal in an insulated state; and a sealing member provided to seal the semiconductor chip, the printed circuit board, and the first conductive block.Type: ApplicationFiled: May 24, 2022Publication date: December 22, 2022Applicant: FUJI ELECTRIC CO., LTD.Inventors: Motohito HORI, Yoshinari IKEDA, Akira HIRAO
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Patent number: 11521925Abstract: A semiconductor module, including a board that has first and second conductive plates located side by side on a first insulating plate, a first external connection terminal located on the first conductive plate, first and second semiconductor chips respectively disposed on the first and second conductive plates, and a printed-circuit board including a second insulating plate and first and second wiring boards located on a first principal plane of the second insulating plate. The first wiring board electrically connects an upper surface electrode of the first semiconductor chip and a relay area on the second conductive plate. The second wiring board is electrically connected to an upper surface electrode of the second semiconductor chip. The semiconductor module further includes a second external connection terminal electrically connected to an end portion of the second wiring board and formed on the second principal plane of the second insulating plate.Type: GrantFiled: October 23, 2020Date of Patent: December 6, 2022Assignee: FUJI ELECTRIC CO., LTD.Inventors: Akira Hirao, Yoshinari Ikeda, Motohito Hori
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Patent number: 11434341Abstract: A resin sheet with a pressure-sensitive adhesive layer including the resin sheet. The resin sheet including a main surface A and a main surface B opposite to each other across a thickness “d”, where the resin sheet has a 50% compression load of 20 N/cm2 or less at 23±5° C. in a direction of the thickness “d”, which is measured in conformity with a method of measuring a compression hardness described in JIS K 6767:1999; where the resin sheet has a Poisson's ratio at 23° C. of 0.10 or less; and the resin sheet has a thickness recovery ratio of 40% or more when compressed by 20% in the direction of the thickness “d” at 23° C.Type: GrantFiled: August 7, 2018Date of Patent: September 6, 2022Assignee: NITTO DENKO CORPORATIONInventors: Yusuke Yamanari, Makoto Saito, Akira Hirao, Kenji Furuta
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Patent number: 11401395Abstract: A resin sheet with a pressure-sensitive adhesive layer including the resin sheet. The resin sheet including a main surface A and a main surface B opposite to each other across a thickness “d”, where the resin sheet has a 50% compression load of 20 N/cm2 or less at 23±5° C. in a direction of the thickness “d”, which is measured in conformity with a method of measuring a compression hardness described in JIS K 6767:1999; where the resin sheet has a Poisson's ratio at 23° C. of 0.10 or less; and the resin sheet has a thickness recovery ratio of 40% or more when compressed by 20% in the direction of the thickness “d” at 23° C.Type: GrantFiled: August 7, 2018Date of Patent: August 2, 2022Assignee: NITTO DENKO CORPORATIONInventors: Yusuke Yamanari, Makoto Saito, Akira Hirao, Kenji Furuta
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Publication number: 20220112410Abstract: The present invention relates to a separation and bonding method for an adherend including: a first bonding step of allowing an adhesive sheet containing at least an electrolyte-containing adhesive layer to bond to a first adherend; a first voltage application step of applying a voltage to the electrolyte-containing adhesive layer to generate a potential difference in a thickness direction of the electrolyte-containing adhesive layer in a state where the electrolyte-containing adhesive layer bonds to the first adherend; a first separation step of separating the adhesive sheet and the first adherend; and a second bonding step of allowing the adhesive sheet separated from the first adherend in the first separation step to bond to a second adherend.Type: ApplicationFiled: September 25, 2019Publication date: April 14, 2022Inventors: Ryo AWANE, Akira HIRAO, Kaori AKAMATSU, Kaori MIZOBATA
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Publication number: 20220077044Abstract: A semiconductor device includes a wiring board that includes a first insulating layer, a first conductive layer arranged over the first insulating layer, a second conductive layer arranged under the first insulating layer, the wiring board further including a magnetic layer that is arranged between the first insulating layer and the first or second conductive layer and that has a higher specific magnetic permeability than the first and second conductive layers, and a carbon layer that is arranged between the first insulating layer and the first or second conductive layer and that has a higher thermal conductivity in a planary direction than the first and second conductive layers; a semiconductor chip electrically connected to the first and second conductive layers; and an insulating circuit board arranged separately from the wiring board and that has the semiconductor chip mounted thereon.Type: ApplicationFiled: August 2, 2021Publication date: March 10, 2022Applicant: Fuji Electric Co., Ltd.Inventors: Takahiro MITSUMOTO, Akira HIRAO, Motohito HORI
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Patent number: 11251163Abstract: A semiconductor device having a semiconductor module that includes a first conductor layer and a second conductor layer facing each other, a group of semiconductor elements that are formed between the first and second conductor layers, and are connected to the second conductor layer respectively via a group of conductor blocks, and a circuit board having one end portion thereof located in a space between the semiconductor elements and the second conductor layer. Each semiconductor element includes first and second main electrodes respectively formed on first and second main surfaces thereof, and a control electrode that is formed on the second main surface. The first main electrode is electrically connected to the first conductor layer. The second main electrode is electrically connected to the second conductor layer via the respective conductor block. The circuit board includes a first wiring layer electrically connected to the control electrodes of the semiconductor elements.Type: GrantFiled: October 29, 2020Date of Patent: February 15, 2022Assignee: FUJI ELECTRIC CO., LTD.Inventors: Motohito Hori, Yoshinari Ikeda, Akira Hirao
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Publication number: 20220032600Abstract: A separation method for an adherend according to the present invention allows members to firmly bond to each other by recovery of adhesive force when a predetermined time elapses after a voltage has been applied and can easily separate the adherend by applying the voltage again, and a bonding method for an adherend according to the present invention allows members to firmly bond to each other by recovery of adhesive force when a predetermined time elapses after a voltage has been applied.Type: ApplicationFiled: September 25, 2019Publication date: February 3, 2022Inventors: Ryo AWANE, Akira HIRAO, Kaori AKAMATSU, Kaori MIZOBATA
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Publication number: 20210193628Abstract: A semiconductor device having a semiconductor module that includes a first conductor layer and a second conductor layer facing each other, a group of semiconductor elements that are formed between the first and second conductor layers, and are connected to the second conductor layer respectively via a group of conductor blocks, and a circuit board having one end portion thereof located in a space between the semiconductor elements and the second conductor layer. Each semiconductor element includes first and second main electrodes respectively formed on first and second main surfaces thereof, and a control electrode that is formed on the second main surface. The first main electrode is electrically connected to the first conductor layer. The second main electrode is electrically connected to the second conductor layer via the respective conductor block. The circuit board includes a first wiring layer electrically connected to the control electrodes of the semiconductor elements.Type: ApplicationFiled: October 29, 2020Publication date: June 24, 2021Applicant: FUJI ELECTRIC CO., LTD.Inventors: Motohito HORI, Yoshinari IKEDA, Akira HIRAO