Abstract: A double-rod type shock absorber includes a rod, first and second pistons held by the rod, first and second piston chambers disposed on an outer side of the first and second pistons, a liquid storage chamber between the first piston and the second piston, a flow path gap formed between an outer peripheral surface of the first and second pistons and an inner peripheral surface of the liquid chamber, and first and second unidirectional flow paths which connect the first and second piston chambers with the liquid storage chamber, wherein, during reciprocating motion of the rod, the unidirectional flow path located on a front side in a movement direction of the rod is closed, and the unidirectional flow path located on a back side in the movement direction of the rod is opened.

Abstract: A double-rod type shock absorber includes a rod, first and second pistons held by the rod, first and second piston chambers disposed on an outer side of the first and second pistons, a liquid storage chamber between the first piston and the second piston, a flow path gap formed between an outer peripheral surface of the first and second pistons and an inner peripheral surface of the liquid chamber, and first and second unidirectional flow paths which connect the first and second piston chambers with the liquid storage chamber, wherein, during reciprocating motion of the rod, the unidirectional flow path located on a front side in a movement direction of the rod is closed, and the unidirectional flow path located on a back side in the movement direction of the rod is opened.

Abstract: A hydraulic shock absorber that can reduce outflow amount of oil by maximally removing an oil film attached to an outer periphery of a rod and that can achieve securement of high slidability between the rod and a rod packing and prevention of wear of the rod packing. A rod packing interposed between an outer periphery of a rod and an inner periphery of a rod-side end wall includes a first lip for scrapping off an oil film attached to the outer periphery of the rod, and a ring-shaped grease holding member for supplying holding grease to the outer periphery of the rod. The grease holding member is in contact with the outer periphery of the rod at a position closer to a rod distal end than the first lip.

Abstract: Provided is a shock absorber enabling stable stop by damping at a terminal of a stroke and covering demanded impact-absorbing models. The shock absorber has a piston chamber, a start part for piston movement, a decelerating part, and an end part for stopping the piston. The start part forms a curve to provide a diameter larger than a virtual tapered surface formed within a stroke range of the piston and to be outward to a central axis of the piston chamber. In the decelerating part, a variation of diameter reduction is increased with the result that the diameter becomes smaller than the tapered surface, and a curve is formed so the change in variation of diameter reduction reaches the maximum variation point and turns negative. In the end part, the variation of diameter reduction is decreased with the result that a curve which enables piston stopping by damping is formed.

Abstract: A hydraulic shock absorber that can reduce outflow amount of oil by maximally removing an oil film attached to an outer periphery of a rod and that can achieve securement of high slidability between the rod and a rod packing and prevention of wear of the rod packing. A rod packing interposed between an outer periphery of a rod and an inner periphery of a rod-side end wall includes a first lip for scrapping off an oil film attached to the outer periphery of the rod, and a ring-shaped grease holding member for supplying holding grease to the outer periphery of the rod. The grease holding member is in contact with the outer periphery of the rod at a position closer to a rod distal end than the first lip.

Abstract: Provided is a shock absorber enabling stable stop by damping at a terminal of a stroke and covering demanded impact-absorbing models. The shock absorber has a piston chamber, a start part for piston movement, a decelerating part, and an end part for stopping the piston. The start part forms a curve to provide a diameter larger than a virtual tapered surface formed within a stroke range of the piston and to be outward to a central axis of the piston chamber. In the decelerating part, a variation of diameter reduction is increased with the result that the diameter becomes smaller than the tapered surface, and a curve is formed so the change in variation of diameter reduction reaches the maximum variation point and turns negative. In the end part, the variation of diameter reduction is decreased with the result that a curve which enables piston stopping by damping is formed.

Abstract: A cylindrically shaped valve rod is housed in a valve hole formed in a cylinder body in a manner so as to be rotatable around a center axis line, and a connecting hole having a first hole opening that is allowed to communicate with a first flow path hole, and a second hole opening that is allowed to communicate with a second flow path hole is formed in the valve rod. A flow adjusting groove that is extending in a circumferential direction around an outer periphery of the valve rod from a position of the first hole opening is formed, and the flow adjusting groove is formed such that a groove width gradually narrows toward a tip end side and the groove depth gradually shallows at the same time, so that the valve opening extent is adjusted along with rotating operation of the valve rod.

Abstract: A cylindrically shaped valve rod is housed in a valve hole formed in a cylinder body in a manner so as to be rotatable around a center axis line, and a connecting hole having a first hole opening that is allowed to communicate with a first flow path hole, and a second hole opening that is allowed to communicate with a second flow path hole is formed in the valve rod. A flow adjusting groove that is extending in a circumferential direction around an outer periphery of the valve rod from a position of the first hole opening is formed, and the flow adjusting groove is formed such that a groove width gradually narrows toward a tip end side and the groove depth gradually shallows at the same time, so that the valve opening extent is adjusted along with rotating operation of the valve rod.

Abstract: A semiconductor device of the invention is formed so that the impurity concentration of a semiconductor substrate (1) under a source diffusion layer (2) is lower than the impurity concentration on a source side of a p-type impurity diffusion layer (6). Therefore, in the semiconductor device of the invention, the junction capacitance of the p-n junction between the source and the substrate is smaller as compared with a conventional LDC structure. In general, the speed of a device is proportional to the product obtained by multiplying together a load capacitance and an inverse of a current value of the device. Accordingly, in the case of applying the present invention to a circuit such as a NAND type CMOS circuit in which a voltage is applied to a region between the source and the substrate, the speed of the device is not decreased. On the other hand, the power consumption of a device is proportional to the product obtained by multiplying together a load capacitance and the square of an applied voltage.

Abstract: A complementary semiconductor device which includes: a semiconductor substrate having a principal surface, with a first region doped with an impurity of a first conductivity type and a second region doped with an impurity of a second conductivity type; a first MOS transistor provided on the second region; and a second MOS transistor provided on the first region. In such a complementary semiconductor device, at least one of the first MOS transistor and the second MOS transistor is an asymmetric MOS transistor of the same conductivity type as the conductivity type of the corresponding region which is either the first region or the second region.

Abstract: A semiconductor device of the invention is formed so that the impurity concentration of a semiconductor substrate under a source diffusion layer is lower than the impurity concentration on a source side of a p-type impurity layer. Therefore, in the semiconductor device of the invention, the junction capacitance of the p-n junction between the source and the substrate is smaller as compared with a conventional LDC structure. In general, the speed of a device is proportional to the product obtained by multiplying together a load capacitance and an inverse of a current value of the device. Accordingly, in the case of applying the present invention to a circuit such as a NAND type CMOS circuit in which a voltage is applied to a region between the source and the substrate, the speed of the device is not decreased. On the other hand, the power consumption of a device is proportional to the product obtained by multiplying together a load capacitance and the square of an applied voltage.

Abstract: A complementary semiconductor device which includes: a semiconductor substrate having a principal surface, with a first region doped with an impurity of a first conductivity type and a second region doped with an impurity of a second conductivity type; a first MOS transistor provided on the second region; and a second MOS transistor provided on the first region. In such a complementary semiconductor device, at least one of the first MOS transistor and the second MOS transistor is an asymmetric MOS transistor of the same conductivity type as the conductivity type of the corresponding region which is either the first region or the second region.

Abstract: A MIS transistor has a semiconductor substrate of a first conduction type; a gate insulation film and a gate electrode which are selectively formed on the semiconductor substrate; an insulating film formed on the side surface of the gate electrode and on the semiconductor substrate; a first gate side wall layer provided on the upper surface and side surface of the insulating film and having a dielectric constant greater than that of the insulating film, the first gate side wall layer having a height smaller than that of the gate electrode; and a second gate side wall layer composed of an insulating film which covers the first gate side wall layer. This MIS transistor can be produced by a known LSI production technique employing self-alignment, without increasing the number of the steps of the process.

Abstract: An unsymmetrical MOS device is disclosed which includes a semiconductor layer of a first conductive type having a surface having a first area and a second area which is offset from the first area; a gate insulator layer located on the first area of the surface of the semiconductor layer; a gate electrode located on the gate insulator layer; and a source region of a second conductive type and a drain region of the second conductive type each located in the semiconductor layer below the second area of the surface. The electric resistance of an area between the first area of the surface and the surface of the source region is smaller than the electric resistance of an area between the first area of the surface and the surface of the drain region.

Abstract: An object of the subject invention is to offer a MOS semiconductor device capable of suppressing hot carrier degradation, improving driving capabilities and also enabling miniaturization to the submicron region and smaller; and methods for its fabrication. By forming the gate electrode 5 through the medium of gate oxide film 4 on one main surface of the first conductivity type semiconductor substrate 1 between the second conductivity type low concentration diffusion layers 3, the effective channel length is made roughly equal to the gate length, and miniaturization to the submicron region and smaller is accomplished.

Abstract: An MOS type semiconductor device comprises a semiconductor substrate including a p-type region doped with p-type impurities and having a surface and an MOS transistor formed in the p-type region, the MOS transistor including: an n-type source region formed in the p-type region; an n-type drain region formed in the p-type region and separated from the n-type source region by a predetermined distance; a channel region formed in the p-type region and located between the n-type source and drain regions; a pair of n-type impurity diffusion regions formed on both sides of the channel region and having an impurity concentration lower than that of the n-type source region; a gate insulating film formed on the surface of the semiconductor substrate, the gate insulating film directly covering the channel region and the pair of n-type impurity diffusion regions; a gate electrode formed on the gate insulating film; and side walls formed on the sides of the gate electrode, wherein each of the side walls has a bottom porti

Abstract: An object of the subject invention is to offer a MOS semiconductor device capable of suppressing hot carrier degradation, improving driving capabilities and also enabling miniaturization to the submicron region and smaller; and methods for its fabrication. By forming the gate electrode 5 through the medium of gate oxide film 4 on one main surface of the first conductivity type semiconductor substrate 1 between the second conductivity type low concentration diffusion layers 3, the effective channel length is made roughly equal to the gate length, and miniaturization to the submicron region and smaller is accomplished.

Abstract: A MIS transistor, has a semiconductor substrate of a first conduction type; a gate insulation film and a gate electrode which are selectively formed on the semiconductor substrate; an insulating film formed on the side surface of the gate electrode and on the semiconductor substrate; a first gate side wall layer provided on the upper surface and side surface of the insulating film and having a dielectric constant greater than that of the insulating film, the first gate side wall layer having a height smaller than that of the gate electrode; and a second gate side wall layer composed of an insulating film which covers the first gate side wall layer. This MIS transistor can be produced by a known LSI production technique employing self-alignment, without increasing the number of the steps of the process.