Abstract: A test pattern generating apparatus comprises a circuit data read in section 11 that divides circuit data into a plurality of functional blocks, a correspondence setting up table preparing section 12 that sorts the plurality of functional blocks into test pattern generating object blocks and test pattern copying object blocks that are configurationally identical with the test pattern generating object blocks and sets up correspondence of the test pattern generating object blocks to the test pattern copying object blocks, a test pattern generating section 13 that generates a test pattern of each of the test pattern generating object blocks and a test pattern copying section 14 that copies the test pattern of each of the test pattern copying object blocks and uses it as test pattern of the test pattern copying object block.

Abstract: A test pattern generating apparatus comprises a circuit data read in section 11 that divides circuit data into a plurality of functional blocks, a correspondence setting up table preparing section 12 that sorts the plurality of functional blocks into test pattern generating object blocks and test pattern copying object blocks that are configurationally identical with the test pattern generating object blocks and sets up correspondence of the test pattern generating object blocks to the test pattern copying object blocks, a test pattern generating section 13 that generates a test pattern of each of the test pattern generating object blocks and a test pattern copying section 14 that copies the test pattern of each of the test pattern copying object blocks and uses it as test pattern of the test pattern copying object block.

Abstract: A single chip microcomputer comprises a central processing unit (CPU) 2, a on-chip RAM 3, a on-chip ROM 5, a first bus DBUS for connecting the CPU, RAM, and ROM with one another and transferring data between them, a second bus ABUS for passing address data corresponding to the data passed through the first bus, a third bus SDBUS for connecting the CPU 2 with the RAM 3 and transferring data between them, the number of bits of the third bus SDBUS being larger than that of the first bus DBUS, and a fourth bus BABUS for connecting the CPU 2 with the RAM 3 and passing address data corresponding to the data passed through the third bus SDBUS. The CPU 2 has a data memory RF serving as general purpose registers for providing internal data to the third bus SDBUS, and a bank specifying register BP for holding positional data of a mapping region in the RAM 3 where the contents of the data memory RF are mapped and providing the positional data to the fourth bus BABUS.

Abstract: A data communication control device controls data transmission between a network bus and a system bus. The data communication control device includes a network bus interface connected to the network bus, a system bus interface connected to the system bus. A port 1 of the two-port memory in an FIFo/RAM is connected to the network bus interface, microprocessor, direct memory access through a first bus. A port 2 of the two-port memory in the FIFo/RAM is connected to the direct memory access through a second bus. The microprocessor is connected to the system bus interface through a third bus. The direct memory access is connected to the system bus interface through a fourth bus.

Abstract: A processor includes a bank-structured memory and is capable of handling multiple interrupts. The processor includes a central processing unit (CPU) comprising a plurality of data memories serving as general-purpose registers, and a plurality of bank specifying registers for use in specifying an address to save and restore data without involving an external system bus which connects the CPU and a program memory, such as a built-in read only memory (ROM), for storing a user program. The processor further includes a bank structured memory, connected to the CPU via an exclusive-use data bus, for holding data stored in the data memories using the bank specifying registers and for returning data stored in the bank structural memory to the data memories using the bank specifying registers.

Abstract: In a data processing apparatus, when making an access to a specific object to be accessed, the data processor supplies an access control signal to a plurality of control signal generators. The data processor further supplies accessed object type data to the accessed object type determining circuit. The determining circuit determines the type of the accessed object on the basis of the accessed object type data, and selectively drives the control signal generator corresponding to the accessed object. The control signal generator driven converts the access control signal into a control signal adapted for the accessed object. An address signal and data are transferred between the specific accessed object supplied with this control signal and the data processor via the address bus and data bus.

Abstract: A communication control device receives and transmits control data and/or communication data through a ring communication network. The apparatus comprises a wait time decision unit for deciding, according to a state of the network, a wait time for detecting a reception of the control data circulating through the network; a wait time holding unit for holding the wait time decided by the wait time decision unit; and a time counting unit for counting time from a reception of the control data and providing a broken control data report signal if the control data is not again received within the wait time.

Abstract: In an address multiplexing apparatus for multiplexing address data to be supplied to 64K bit, 256K bit, and 1M bit DRAMs, upon multiplexing of address data, input address data of 20 bits are classified into two groups, i.e., the lower 16 bits and the upper 4 bits. The lower 16-bit group is multiplexed so that the upper 8 bits serve as row address data, and the remaining lower 8 bits serve as column address data. In the upper 4-bit group, adjacent bits are multiplexed. The apparatus can be commonly used for the three memories having different capacities with the simple circuit arrangement, and page mode access can be executed.

Abstract: A logic circuit comprises an input register for holding data to be computed, a computation circuit for computationally processing the data inputted from the input register to output the computationally processed result, and an output register for holding the computationally processed result outputted from the computation circuit, characterized in that the computation circuit includes computational data pass device for passing input data therethrough as it is without applying computation processing thereto, thus permitting data held in the input register to pass through the computation circuit and be inputted to the output register as it is. By simply varying the control inputs to the register and the computation circuit, it is possible to read data from an arbitrary register or write it thereinto. This easily gives a test without practically increasing an amount of wiring.

Abstract: A logic circuit having a plurality of macrocells for processing test input data and outputting a result of the process. Each of the macrocells is tested independently of each other and includes an input-output circuit. The input-output circuit comprises: a first holding register for holding the test input data; a selector circuit for shutting off an input path for normal operation signals to the macrocell in question at the time of testing the macrocell, selecting the test input data held in the first holding register, and outputting the selected test input data to a logic circuit to be tested in the macrocell; a second holding register for holding test output data obtained as a result of a test process carried out in the macrocell based on the test input data, and outputting the test output data externally; and a switching circuit for shutting off, at the time of testing the macrocell, an output path for normal operation signals from the microcell to other portions of the logic circuit.

Abstract: In a system including LSIs, the signature register used for self-testing the LSI functions is assigned to one register accessible by a machine instruction. The signature is calculated in the self-test operation, and the calculation result is updated depending on the result from the execution of the machine instruction. With the above technical idea, the test function for the LSI function is available not only for the test mode, but also for the normal operation. This simplifies the self-test program for testing the functions of the application system.

Abstract: A logic integrated circuit includes a FIFO type memory circuit provided for testing. A logic value at each test node is stored in the memory circuits during a write-in enable period set by a control signal from a flip-flop or an externally supplied control signal, and the memory data is read out from the memory circuits, to trace the output states of internal bus, register, multiplier, and the like.

Abstract: A logic circuit which can easily perform a logical function test is disclosed. A first type of the logic circuit comprises a combinational circuit having a plurality of internal nodes, node data latch circuits respectively connected to the preselected internal nodes for latching their logical states, and readout means for reading data latched in the latch circuits by using a data transfer clock. Further, there may be adopted implementation such that the node data latch circuit functions to allow a predetermined node to be placed in the logical state latched in the node data latch circuit. Thus, this first type of the logic circuit makes it possible to monitor even logical states of internal nodes of the combinational circuit. A second type of the logic circuit comprises a combinational circuits, a plurality of memory means, designation means e.g.

Abstract: An integrated circuit (IC) of the invention is provided with a plural sets of power supply and ground lines within a package of the IC. Circuit elements, e.g., output buffers in the IC are divided into plural groups and each buffer group is coupled to the corresponding set of the power supply and ground lines. Each set of the power supply and ground lines is provided with independent wirings so that the magnitude of current change in each wiring and the value of each wiring inductance become small.

Abstract: In a floating-point arithmetic operation system performing an arithmetic operation on two given operands X, Y and providing the result Z of the arithmetic operation, the operands X and Y are each classified according to their attributes; and, at least part of the bits of the operand X, at least part of the bits of the operand Y or a predetermined set of bits are adopted as at least part of the result Z of the operation when the results of the classifications are one of predetermined combinations.

Abstract: In floating-point multiplication, the sum of the exponents of the two operands is determined by the use of a single adder. The exponents are modified either before they are inputted to the adder or at the output of the adder. A carry signal of "1" is applied whenever addition is carried out. A signal indicative of occurrence of underflow or overflow is also obtained.

Abstract: A data output circuit provided with data input terminals to which n-bit logic data is supplied, a latching section for holding this logic data, and output buffers for outputting in parallel the logic data held in the latching section.The data output circuit further includes exclusive OR gates for detecting the non-coincidence between each of 1-bit signals applied from the data input terminals and its corresponding one of 1-bit output signals applied from the latching section; a majority circuit for generating an inversion control signal in response to the non-coincidences whose number is larger than n/2; and a circuit for generating a logic notation signal, synchronized with the data held in the latching section. The latching section holds the inverted replica of logic signals applied from the data input terminals in response to the inversion control signal.

Abstract: In a priority assignment circuit receiving service request signals and comprising a plurality of service enable signal transmission units for transmitting a service enable signal in accordance with a priority determined by priority signals, bypass circuits are provided each for a predetermined number of service request units. Each bypass circuit is adapted to pass the service enable signal when respective service request signals are not coupled to them from service request units.

Abstract: There is disclosed an arithmetic operation circuit including an adder for performing a multiplication and a division. A one stage arithmetic cell group is formed by connecting eight arithmetic cells. Eight stage arithmetic cell groups are set in the obliquely shifted arrangement and a ninth arithmetic cell group is provided corresponding to the shifts of their arithmetic cell groups in the array. A partial carry circuit is connected to the respective arithmetic cell groups. The arithmetic cells are all comprised of complementary MOS gates and the carry circuit is comprised of enhancement/depletion type MOS gates.

Abstract: Disclosed is a substrate bias generator circuit which comprises an oscillator circuit, a driving circuit producing a rectangular-wave signal in accordance with an oscillation output signal from the oscillator circuit, and a charge pump circuit pumping electric charges into a substrate in accordance with the rectangular-wave output signal from the driving circuit. The oscillator circuit is a voltage-controlled oscillator circuit whose oscillation frequency is controlled in accordance with a substrate bias voltage from the charge pump circuit.