Abstract: A battery anomaly detection device includes: an alternating-current (AC) impedance measurer that measures AC impedance of a battery cell; and an anomaly determiner that determines whether the AC impedance is within a reference range, and when the AC impedance is not within the reference range, determines that the battery cell is an anomalous cell.

Abstract: A voltage measuring apparatus is configured to measure voltages of respective battery cells of a battery cell array including a plurality of battery cell groups each including a predetermined number of battery cells connected in series. The voltage measuring apparatus includes a plurality of measuring units each provided for each of the battery cell groups. The adjacent measuring units are connected through a communication channel so as to perform current communication therebetween. A bidirectional diode circuit element is connected to the communication channel extending between the adjacent measuring units.

Abstract: A voltage measuring apparatus is configured to measure voltages of respective battery cells of a battery cell array including a plurality of battery cell groups each including a predetermined number of battery cells connected in series. The voltage measuring apparatus includes a plurality of measuring units each provided for each of the battery cell groups. The adjacent measuring units are connected through a communication channel so as to perform current communication therebetween. A bidirectional diode circuit element is connected to the communication channel extending between the adjacent measuring units.

Abstract: A voltage measuring apparatus is configured to measure voltages of respective battery cells of a battery cell array including a plurality of battery cell groups each including a predetermined number of battery cells connected in series. The voltage measuring apparatus includes a plurality of measuring units each provided for each of the battery cell groups. The adjacent measuring units are connected through a communication channel so as to perform current communication therebetween. A bidirectional diode circuit element is connected to the communication channel extending between the adjacent measuring units.

Abstract: A voltage measuring apparatus is configured to measure voltages of respective battery cells of a battery cell array including a plurality of battery cell groups each including a predetermined number of battery cells connected in series. The voltage measuring apparatus includes a plurality of measuring units each provided for each of the battery cell groups. The adjacent measuring units are connected through a communication channel so as to perform current communication therebetween. A bidirectional diode circuit element is connected to the communication channel extending between the adjacent measuring units.

Abstract: A voltage measuring apparatus is configured to measure voltages of respective battery cells of a battery cell array including a plurality of battery cell groups each including a predetermined number of battery cells connected in series. The voltage measuring apparatus includes a plurality of measuring units each provided for each of the battery cell groups. The adjacent measuring units are connected through a communication channel so as to perform current communication therebetween. A bidirectional diode circuit element is connected to the communication channel extending between the adjacent measuring units.

Abstract: A voltage measuring apparatus is configured to measure voltages of respective battery cells of a battery cell array including a plurality of battery cell groups each including a predetermined number of battery cells connected in series. The voltage measuring apparatus includes a plurality of measuring units each provided for each of the battery cell groups. The adjacent measuring units are connected through a communication channel so as to perform current communication therebetween. A bidirectional diode circuit element is connected to the communication channel extending between the adjacent measuring units.

Abstract: A voltage measuring apparatus is configured to measure voltages of respective battery cells of a battery cell array including a plurality of battery cell groups each including a predetermined number of battery cells connected in series. The voltage measuring apparatus includes a plurality of measuring units each provided for each of the battery cell groups. The adjacent measuring units are connected through a communication channel so as to perform current communication therebetween. A bidirectional diode circuit element is connected to the communication channel extending between the adjacent measuring units.

Abstract: A voltage measuring apparatus is configured to measure voltages of respective battery cells of a battery cell array including a plurality of battery cell groups each including a predetermined number of battery cells connected in series. The voltage measuring apparatus includes a plurality of measuring units each provided for each of the battery cell groups. The adjacent measuring units are connected through a communication channel so as to perform current communication therebetween. A bidirectional diode circuit element is connected to the communication channel extending between the adjacent measuring units.

Abstract: A voltage measuring apparatus is configured to measure voltages of respective battery cells of a battery cell array including a plurality of battery cell groups each including a predetermined number of battery cells connected in series. The voltage measuring apparatus includes a plurality of measuring units each provided for each of the battery cell groups. The adjacent measuring units are connected through a communication channel so as to perform current communication therebetween. A bidirectional diode circuit element is connected to the communication channel extending between the adjacent measuring units.

Abstract: A actuator driver includes a digital filter configured to perform phase compensation of a digital torque command signal using a fed-back digital signal; a digital PWM generator configured to generate a plurality of pulse-width modulated PWM control signals in response to an output of the digital filter; at least one H bridge configured to select and output a first or second terminal voltage in response to the plurality of PWM control signals; first and second continuous time ?? A/D converters configured to convert the first and second terminal voltages from analog to digital, respectively; and a feed-back filter configured to decimate outputs of the first and second continuous time ?? A/D converters to feed back the digital signal to the digital filter.

Abstract: A voltage measuring apparatus is configured to measure voltages of respective battery cells of a battery cell array including a plurality of battery cell groups each including a predetermined number of battery cells connected in series. The voltage measuring apparatus includes a plurality of measuring units each provided for each of the battery cell groups. The adjacent measuring units are connected through a communication channel so as to perform current communication therebetween. A bidirectional diode circuit element is connected to the communication channel extending between the adjacent measuring units.

Abstract: A actuator driver includes a digital filter configured to perform phase compensation of a digital torque command signal using a fed-back digital signal; a digital PWM generator configured to generate a plurality of pulse-width modulated PWM control signals in response to an output of the digital filter; at least one H bridge configured to select and output a first or second terminal voltage in response to the plurality of PWM control signals; first and second continuous time ?? A/D converters configured to convert the first and second terminal voltages from analog to digital, respectively; and a feed-back filter configured to decimate outputs of the first and second continuous time ?? A/D converters to feed back the digital signal to the digital filter.

Abstract: In each stage, a digital signal corresponding to a portion of bits is generated from an input analog signal, an analog reference signal is generated by a DA conversion portion (7, 8) based on the digital signal, and a remainder operation on the input analog signal is performed by a remainder operation portion (9). A test can be performed by supplying a test signal in place of the input analog signal. A control portion (14a) performs control, in a test mode, to stop supply of the input analog signal to the remainder operation portion and stop the reference voltage selection of the DA conversion portion based on the digital signal, while performing reference voltage selection based on a DA conversion control signal for use in testing, thereby supplying the remainder operation portion with the test signal composed of predetermined one of the reference voltages, in place of the input analog signal, and the analog reference signal.

Abstract: Multiple stages sequentially convert respective input analog signals to partial digital data. Each stage includes: a partial A/D converter; a partial D/A converter; an adder that adds/subtracts the analog signal from the previous stage and an output from the partial D/A converter; and a gain amplifier that amplifies an output of the adder and supplies to the next stage. The pipelined A/D converter further includes: a correction value adding unit that adds a correction value to the output from the decoder unit; a correction value calculating unit that, based on the output from the correction value adding unit, calculates an error between the median of the output data and an ideal median at two points in the stage input/output characteristics, saves the calculated value as the correction value and supplies it to the correction value adding unit; and a control unit that controls the above units so as to perform the correction operation.

Abstract: A PLL circuit comprises a phase frequency detector configured to output a phase frequency difference signal with a pulse duration according to a phase difference and a frequency difference between a reference clock signal and a feedback clock signal according to an output clock signal; a charge pump circuit configured to output a charge pump current which is an output current according to the phase frequency difference signal and reduce a charge pump current amount in accordance with a charge pump current amount control signal for reducing the charge pump current amount stepwisely; and a lock detecting unit configured to detect whether or not the feedback clock signal is locked to the reference clock signal and output a lock detection signal when detecting a lock of the reference clock signal and the feedback clock signal

Abstract: Multiple stages sequentially convert respective input analog signals to partial digital data. Each stage includes: a partial A/D converter; a partial D/A converter; an adder that adds/subtracts the analog signal from the previous stage and an output from the partial D/A converter; and a gain amplifier that amplifies an output of the adder and supplies to the next stage. The pipelined A/D converter further includes: a correction value adding unit that adds a correction value to the output from the decoder unit; a correction value calculating unit that, based on the output from the correction value adding unit, calculates an error between the median of the output data and an ideal median at two points in the stage input/output characteristics, saves the calculated value as the correction value and supplies it to the correction value adding unit; and a control unit that controls the above units so as to perform the correction operation.

Abstract: In each stage, a digital signal corresponding to a portion of bits is generated from an input analog signal, an analog reference signal is generated by a DA conversion portion (7, 8) based on the digital signal, and a remainder operation on the input analog signal is performed by a remainder operation portion (9). A test can be performed by supplying a test signal in place of the input analog signal. A control portion (14a) performs control, in a test mode, to stop supply of the input analog signal to the remainder operation portion and stop the reference voltage selection of the DA conversion portion based on the digital signal, while performing reference voltage selection based on a DA conversion control signal for use in testing, thereby supplying the remainder operation portion with the test signal composed of predetermined one of the reference voltages, in place of the input analog signal, and the analog reference signal.

Abstract: In a playback signal processing device for extracting, from an analog playback signal, playback data and a clock synchronized with the playback data, a digital equalizer 2 is disposed outside a clock extraction loop formed by an interpolator 3, a timing recovery circuit 4, and a control circuit 5. The digital equalizer 2 is provided between an A/D converter 1 and the interpolator 3 and performs equalization processing on digital playback data from the A/D converter 1 in accordance with the timing of a fixed clock CLK from a synthesizer 7. The coefficients of the digital equalizer 2 are updated by the control circuit 5 by using a coefficient setting device 6 according to frequency ratio information 4a from the timing recovery circuit 4. Accordingly, the clock extraction capability is enhanced in spite of the equalization processing on the playback signal by the digital equalizer.

Abstract: A digital analog converter includes a current conversion section and a voltage conversion section. The current conversion section has a first output terminal and a second output terminal. The first output terminal outputs a first current and a second output terminal outputs a second current, the first current varying in value according to inputted digital data, the sum of the first current and the second current becoming a constant current. The voltage conversion section converts the first current to a corresponding first voltage and produces an offset voltage on the basis of the constant current and outputs the sum of the first voltage and the offset voltage as an output voltage.