Patents by Inventor Akira Matsudaira
Akira Matsudaira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11462608Abstract: An electronic device may include a display with pixels formed using light-emitting diodes, thin-film silicon transistors, thin-film semiconducting-oxide transistors, and capacitors. The silicon transistors, semiconducting-transistors, and capacitors may have control terminals that are coupled to gate or routing lines that extend across the face of the display and that are formed in a low resistance source-drain metal routing layer. Forming routing/gate lines using the low resistance source-drain metal routing layer dramatically reduces the resistance of the gate lines, which enables better timing margins for large display panels operating at higher refresh rates.Type: GrantFiled: January 7, 2021Date of Patent: October 4, 2022Assignee: Apple Inc.Inventors: Shinya Ono, Chin-Wei Lin, Akira Matsudaira, Jiun-Jye Chang, Jung Yen Huang, Pei-En Chang, Rungrot Kitsomboonloha, Szu-Hsien Lee
-
Publication number: 20220181418Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated semiconducting oxide transistors. The semiconducting oxide transistors may exhibit different device characteristics. Some of the semiconducting oxide transistors may be formed using a first oxide layer formed from a first semiconducting oxide material using first processing steps, whereas other semiconducting oxide transistors are formed using a second oxide layer formed from a second semiconducting oxide material using second processing steps different than the first processing steps. The display may include three or more different semiconducting oxide layers formed during different processing steps.Type: ApplicationFiled: October 18, 2021Publication date: June 9, 2022Inventors: Jung Yen Huang, Shinya Ono, Chin-Wei Lin, Akira Matsudaira, Cheng Min Hu, Chih Pang Chang, Ching-Sang Chuang, Gihoon Choo, Jiun-Jye Chang, Po-Chun Yeh, Shih Chang Chang, Yu-Wen Liu, Zino Lee
-
Patent number: 11210990Abstract: An electronic device may have a display and a gaze tracking system. The electronic device may display images on the display that have a higher resolution in a portion of the display that overlaps a gaze location than other portions of the display. Timing controller circuitry and column driver circuitry may include interpolation and filter circuitry. The interpolation and filter circuitry may be used to perform nearest neighbor interpolation and two-dimensional spatial filtering on low resolution image data. Display driver circuitry may be configured to load higher resolution data into selected portions of a display. The display driver circuitry may include low and high resolution image data buffers and configurable row driver circuitry. Block enable transistors may be included in a display to allow selected blocks of pixels to be loaded with high resolution image data.Type: GrantFiled: August 15, 2017Date of Patent: December 28, 2021Assignee: Apple Inc.Inventors: Ivan Knez, Cheuk Chi Lo, Akira Matsudaira, Chun-Yao Huang, Giovanni Carbone, Paolo Sacchetto, Chaohao Wang, Sheng Zhang, Adam Adjiwibawa
-
Publication number: 20210305353Abstract: An electronic device may include a display with pixels formed using light-emitting diodes, thin-film silicon transistors, thin-film semiconducting-oxide transistors, and capacitors. The silicon transistors, semiconducting-transistors, and capacitors may have control terminals that are coupled to gate or routing lines that extend across the face of the display and that are formed in a low resistance source-drain metal routing layer. Forming routing/gate lines using the low resistance source-drain metal routing layer dramatically reduces the resistance of the gate lines, which enables better timing margins for large display panels operating at higher refresh rates.Type: ApplicationFiled: January 7, 2021Publication date: September 30, 2021Inventors: Shinya Ono, Chin-Wei Lin, Akira Matsudaira, Jiun-Jye Chang, Jung Yen Huang, Pei-En Chang, Rungrot Kitsomboonloha, Szu-Hsien Lee
-
Patent number: 10355007Abstract: A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.Type: GrantFiled: December 15, 2016Date of Patent: July 16, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Xiying Costa, Dana Lee, Yanli Zhang, Johann Alsmeier, Yingda Dong, Akira Matsudaira
-
Publication number: 20190180672Abstract: An electronic device may have a display and a gaze tracking system. The electronic device may display images on the display that have a higher resolution in a portion of the display that overlaps a gaze location than other portions of the display. Timing controller circuitry and column driver circuitry may include interpolation and filter circuitry. The interpolation and filter circuitry may be used to perform nearest neighbor interpolation and two-dimensional spatial filtering on low resolution image data. Display driver circuitry may be configured to load higher resolution data into selected portions of a display. The display driver circuitry may include low and high resolution image data buffers and configurable row driver circuitry. Block enable transistors may be included in a display to allow selected blocks of pixels to be loaded with high resolution image data.Type: ApplicationFiled: August 15, 2017Publication date: June 13, 2019Inventors: Ivan Knez, Cheuk Chi Lo, Akira Matsudaira, Chun-Yao Huang, Giovanni Carbone, Paolo Sacchetto, Chaohao Wang, Sheng Zhang, Adam Adjiwibawa
-
Publication number: 20170098655Abstract: A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.Type: ApplicationFiled: December 15, 2016Publication date: April 6, 2017Inventors: Xiying COSTA, Dana LEE, Yanli ZHANG, Johann ALSMEIER, Yingda DONG, Akira MATSUDAIRA
-
Patent number: 9589839Abstract: Corner rounding of electrically conductive layers in a replacement electrode integration scheme can be alleviated by employing compositionally modulated sacrificial material layers. An alternating stack of insulating layers and compositionally modulated sacrificial material layers can be formed over a substrate. Each of the compositionally modulated sacrificial material layers has a vertical modulation of material composition such that each compositionally modulated sacrificial material layer provides greater resistance to conversion into a silicon-oxide-containing material at upper and lower portions thereof than at a middle portion thereof during a subsequent oxidation process. Bird's beak features can be formed with lesser dimensions, and electrically conductive layers formed by replacement of remaining portions of the sacrificial material layers with a conductive material can have less corner rounding.Type: GrantFiled: February 1, 2016Date of Patent: March 7, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Yusuke Ikawa, Kiyohiko Sakakibara, Eisuke Takii, Kengo Kajiwara, Seiji Shimabukuro, Akira Matsudaira, Hiroyuki Ogawa
-
Patent number: 9576971Abstract: A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.Type: GrantFiled: December 9, 2014Date of Patent: February 21, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Yanli Zhang, Johann Alsmeier, Yingda Dong, Akira Matsudaira
-
Patent number: 9553146Abstract: A monolithic three dimensional NAND string includes a semiconductor channel, where at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, an interlevel insulating layer located between adjacent control gate electrodes, a blocking dielectric layer located in contact with the plurality of control gate electrodes and an interlevel insulating layer, a charge storage layer located at least partially in contact with the blocking dielectric layer, and a tunnel dielectric located between the charge storage layer and the semiconductor channel. The charge storage layer has a curved profile.Type: GrantFiled: June 5, 2014Date of Patent: January 24, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Yanli Zhang, Matthias Baenninger, Akira Matsudaira, Yao-Sheng Lee, Johann Alsmeier
-
Patent number: 9552991Abstract: A method of making a monolithic three dimensional NAND string includes providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, etching the stack to form at least one trench in the stack, forming a blocking dielectric over a side wall of the at least one trench, forming a charge storage layer over the blocking dielectric in the at least one trench, forming a tunnel dielectric over the charge storage layer in the at least one trench and forming a semiconductor channel over the tunnel dielectric in the at least one trench.Type: GrantFiled: April 30, 2014Date of Patent: January 24, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Akira Matsudaira, James Kai, Yuan Zhang, Vinod Purayath, Donovan Lee
-
Patent number: 9543139Abstract: Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be used to provide lateral support between closely spaced device structures to prevent collapsing of the closely spaced device structures during an etching process (e.g., during a word line etch). In one example, during fabrication of a NAND flash memory, one or more mechanical support structures may be in place prior to performing a high aspect ratio word line etch or may be formed during the word line etch. In some cases, the one or more mechanical support structures may comprise portions of an inter-poly dielectric (IPD) layer that were in place prior to performing the word line etch.Type: GrantFiled: April 7, 2014Date of Patent: January 10, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Akira Matsudaira, Donovan Lee
-
Publication number: 20160163729Abstract: A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.Type: ApplicationFiled: December 9, 2014Publication date: June 9, 2016Inventors: Yanli ZHANG, Johann ALSMEIER, Yingda DONG, Akira MATSUDAIRA
-
Publication number: 20160163389Abstract: A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.Type: ApplicationFiled: December 9, 2014Publication date: June 9, 2016Inventors: Yanli ZHANG, Johann ALSMEIER, Yinda DONG, Akira MATSUDAIRA
-
Patent number: 9355727Abstract: A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.Type: GrantFiled: December 9, 2014Date of Patent: May 31, 2016Assignee: SANDISK TECHNOLOGIES INC.Inventors: Yanli Zhang, Johann Alsmeier, Yinda Dong, Akira Matsudaira
-
Patent number: 9224746Abstract: A non-volatile memory system, comprising non-volatile storage device with word lines having an inverted T-shape over floating gates. The inverted T-shape shape has a wider bottom portion and a thinner top portion. The thinner top portion increases the separation between adjacent word lines relative to the separation between the wider bottom portions. An air gap may separate adjacent word lines. The thinner top portion of the word lines increases the path length between adjacent word lines. The likelihood of word line to word line short may be decreased by reducing the electric field between adjacent word lines.Type: GrantFiled: November 5, 2013Date of Patent: December 29, 2015Assignee: SanDisk Technologies Inc.Inventors: Vinod R. Purayath, James Kai, Donovan Lee, Yuan Zhang, Akira Matsudaira
-
Publication number: 20150357413Abstract: A monolithic three dimensional NAND string includes a semiconductor channel, where at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, an interlevel insulating layer located between adjacent control gate electrodes, a blocking dielectric layer located in contact with the plurality of control gate electrodes and an interlevel insulating layer, a charge storage layer located at least partially in contact with the blocking dielectric layer, and a tunnel dielectric located between the charge storage layer and the semiconductor channel. The charge storage layer has a curved profile.Type: ApplicationFiled: June 5, 2014Publication date: December 10, 2015Applicant: SanDisk Technologies Inc.Inventors: Yanli Zhang, Matthias Baenninger, Akira Matsudaira, Yao-Sheng Lee, Johann Alsmeier
-
Patent number: 9209031Abstract: A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to memory holes at a bottom of a stack. The stack includes alternating control gate layers and dielectric layers on a substrate, and memory holes are etched through the stack. The process avoids the need to etch through films at the bottom of the memory hole. Instead, a path is formed from the bottom of the memory hole to the top of the stack. The path includes a horizontal portion using a voided trench in a substrate dielectric, and a passageway etched in the stack. The memory films, a channel material and a dielectric material are deposited throughout the interior surfaces of the void and the memory holes concurrently. The path is filled with metal to form a continuous, low resistance conductive path.Type: GrantFiled: March 7, 2014Date of Patent: December 8, 2015Assignee: SanDisk Technologies Inc.Inventors: Matthias Baenninger, Johann Alsmeier, Akira Matsudaira, Jayavel Pachamuthu
-
Publication number: 20150318298Abstract: A method of making a monolithic three dimensional NAND string includes providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, etching the stack to form at least one trench in the stack, forming a blocking dielectric over a side wall of the at least one trench, forming a charge storage layer over the blocking dielectric in the at least one trench, forming a tunnel dielectric over the charge storage layer in the at least one trench and forming a semiconductor channel over the tunnel dielectric in the at least one trench.Type: ApplicationFiled: April 30, 2014Publication date: November 5, 2015Applicant: SanDisk Technologies, Inc.Inventors: Akira Matsudaira, James Kai, Yuan Zhang, Vinod Purayath, Donovan Lee
-
Publication number: 20150318295Abstract: A method of making a monolithic three dimensional NAND string includes providing a stack of alternating insulating layers and control gate films over a major surface of a substrate. Each of the control gate films includes a middle layer located between a first control gate layer and a second control gate layer, the middle layer being a different material from the first and second control gate layers and from the insulating layers. The method also includes forming a front side opening in the stack, and forming a blocking dielectric, at least one charge storage region, a tunnel dielectric and a semiconductor channel in the front side opening in the stack.Type: ApplicationFiled: April 30, 2014Publication date: November 5, 2015Applicant: SanDisk Technologies, Inc.Inventors: James Kai, Vinod Purayath, Donovan Lee, Akira Matsudaira