Abstract: In a data processor having a box type unit in which a keyboard and a folding display are incorporated, the data processor includes a main unit which has a receiver for wireless signals on an external side wall close to a supporter for pivotally supporting the folding display, and an auxiliary input apparatus having a case unit and a wireless signal transmitting unit at a corner of said case unit which is opposed to the receiving unit of said main unit when juxtaposed with said keyboard.

Abstract: A flat keyboard arrangement includes a color of blocks. Each block corresponds to a key unit and is liquid crystal display having a screen divided into a number capable of producing any natural color. A table is provided for storing color data of the blocks, and for storing function data representing the function assigned to blocks. A driver circuit is provided for driving the color liquid crystal display to illuminate one or more colors in accordance with the data stored in the table. A transparent touch switch arrangement is placed on the color liquid crystal display. The transparent touch switch arrangement has transparent sheet in which a plurality of transparent touch switches are located correspondingly to the blocks of the screen to define touch keys.

Abstract: An electronic cash register includes a mask ROM for memorizing a fixed operation program. First through third RAM's are provided for storing information for partly modifying the operation program memorized in the mask ROM. The first RAM stores information which indicates an address of the mask ROM at which the program should be modified. The second RAM stores a modified program. The third RAM stores an address table which correlates the address of the mask ROM at which the address should be modified, and the addresses of the second RAM at which the modified program is stored. A control system performs an operation in accordance with the operation program memorized in the the mask ROM with reference to the first RAM. When the first RAM indicates the modification, the operation is conducted in accordance with the modified program information and associated address table stored in the second and third RAM's.

Abstract: An FS signal demodulator includes a zero-crossing detector which detects zero-crossings of frequency shift signals (FS), a pulse converter which generates a train of "0" and "1", "0" representative of a time slot from the first detected zero-crossing through a given period of time and "1" representative of a time slot from that period through the next succeeding zero-crossing, a memory means receiving the outputs of the pulse converter and thus containing the train of the pulses with the length corresponding to modulation rate, a counter means counting the number of "1's" or "0's" contained within the memory means in response to clock signals, and a determination circuit which effects frequency discrimination by comparing the counts of the counter means with a given limit.

Abstract: In obtaining a sinusoidal waveform signal of a predetermined frequency, a rectangular waveform signal having a frequency four times higher than the pedetermined frequency of the sinusoidal waveform signal is provided and then subjected to frequency divisions of 1/2 and 1/4 through the use of a couple of binary counters. While the original rectangular waveform signal and the 1/2 frequency divided rectangular waveform signal are both passed through an EXCLUSIVE OR circuit, the 1/2 frequency divided and 1/4 frequency divided rectangular waveform signals are passed through another EXCLUSIVE OR circuit. Both of the outputs of the EXCLUSIVE OR circuits are added to develop a desired step waveform signal, after being evaluated at different weights. The generation of the predetermined sinusoidal waveform signal is achieved by filtering the thus obtained step waveform signal.