Abstract: In a semiconductor device having MOS transistors, protective elements are connected to gate electrodes 5-b and 5-c each of which is an independent gate electrode through the first aluminum layers 7-a and 7-d. The first aluminum layers 7-a and 7-d are the wiring layers of the lowest layer. The protective elements are constituted by a junction of N well 1 and P+ diffused layer 3-f and a junction of P well 2 and N+ diffused layer 4-f, and a junction of N well 1 and P+ diffused layer 3-g and a junction of P well 2 and N+ diffused layer 4-g.

Abstract: An integrated circuit device capable of testing manufacturing errors such as variations in dimensions at a masking step or the like or misalignment at an alignment step in a plurality of directions with a test circuit having a monitor transistor. The integrated circuit device has a functional circuit for performing a function assigned to the integrated circuit device and a test circuit. The test circuit comprises a plurality of MIS (Metal-Insulator-Semiconductor) transistors each having a gate electrode projecting from a gap between a source region and a drain region, respective gate electrodes projecting in directions different from one another. Typically, the integrated circuit device has a rectangular shape in which the test circuit is disposed inside of each vertex thereof. The test circuit is typically formed from four MOS (Metal-Oxide-Semiconductor) transistors having gate electrodes projecting in directions different from one another by approximately 90 degrees.

Abstract: An integrated circuit device capable of testing manufacturing errors such as variations in dimensions at a masking step or the like or misalignment at an alignment step in a plurality of directions with a test circuit having a monitor transistor. The integrated circuit device has a functional circuit for performing a function assigned to the integrated circuit device and a test circuit. The test circuit comprises a plurality of MIS (Metal-Insulator-Semiconductor) transistors each having a gate electrode projecting from a gap between a source region and a drain region, respective gate electrodes projecting in directions different from one another. Typically, the integrated circuit device has a rectangular shape in which the test circuit is disposed inside of each vertex thereof. The test circuit is typically formed from four MOS (Metal-Oxide-Semiconductor) transistors having gate electrodes projecting in directions different from one another by approximately 90 degrees.

Abstract: A semiconductor device has electrostatic protection device capable of preventing characteristic fluctuation of MOS transistor caused by electrostatic discharge. PN junction is formed in between N+ cathode region and boron upward diffusion region of P+ substrate, thus being formed low breakdown voltage diode whose breakdown occurs at low reverse voltage. The diode is in use as electrostatic protection device of either input circuit or output circuit so that it is capable of protecting internal device transistor efficiently from applied surge when gate oxide film becomes thin film.

Abstract: A semiconductor device is provided and contains a semiconductor substrate, a first transistor, and a second transistor. The first transistor is formed on the semiconductor substrate and has a first gate electrode. The second transistor is formed on the semiconductor substrate and has a second gate electrode. Also, the thickness of the first gate electrode is different than the thickness of the second gate electrode. Also, a method for forming the semiconductor device is provided.

Abstract: A semiconductor device is provided and contains a semiconductor substrate, a first transistor, and a second transistor. The first transistor is formed on the semiconductor substrate and has a first gate electrode. The second transistor is formed on the semiconductor substrate and has a second gate electrode. Also, the thickness of the first gate electrode is different than the thickness of the second gate electrode. Also, a method for forming the semiconductor device is provided.

Abstract: An electrostatic protection device for use in a semiconductor integrated circuit, includes a base region of a first conductivity type formed at a principal surface of a semiconductor substrate, a plurality of collector regions constituted of a plurality of first diffused regions of a second conductivity type opposite to the first conductivity type. The first diffused regions are formed on a surface of the base region in the form of a plurality of strips parallel to each other but separate from each other. Emitter regions are constituted of a second diffused region of the second conductivity type formed in the form of a strip between each pair of adjacent collector regions of the plurality of collector regions and a third diffused region of the second conductivity type formed under a contact hole formed in at least one portion of a boundary region at a side of the second diffused region adjacent to the collector region, the third diffused region being connected to the second diffused region.

Abstract: A semiconductor integrated circuit is manufactured in the following steps. A first silicon oxide film is formed on a silicon substrate. A silicon nitride film is formed on the first silicon oxide film. A second silicon oxide film is formed on the silicon nitride film. The second silicon oxide film is patterned by isotropic etching. The silicon nitride film is etched by using the patterned second silicon oxide film as a mask. A first region having one conductivity type is selectively formed in the silicon substrate by using the second silicon oxide film as a mask. An outer peripheral region of the second silicon oxide film is isotropically etched. The silicon nitride film is etched by using the second silicon oxide film, whose outer peripheral region is etched, as a mask. A third silicon oxide film is formed by a selective oxidation method using the remaining silicon nitride film as a mask. The silicon nitride film is removed.