Abstract: A driving assistance device includes a memory and a processor. The processor acquires travel information including acceleration of a moving body. The processor presents, to the moving body, information regarding cargo collapse on the moving body that is specified on the basis of a distribution of the acceleration of the moving body in multiple axes on the basis of the travel information.

Abstract: An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.

Abstract: An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.

Abstract: An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.

Abstract: A method and structure for a dynamic random access device which includes a substrate having a trench, a conductor in the trench, a transistor adjacent the trench and a conductive strap electrically connecting the conductor and the transistor, wherein the strap comprises a plurality of strap conductors and the strap has a lower resistance than the conductor. The conductor comprises a first material having a first resistance and the strap comprises a second material different than the first material having a second resistance, wherein the second resistance is lower than the first resistance. The plurality of strap conductors comprises at least two electrically connected strap conductors, and a first strap conductor is adjacent the conductor and a second strap conductor is adjacent the transistor and the first strap conductor has an improved interface with the conductor. The strap comprises a lip strap, wherein the strap forms an L-shape.

Abstract: A memory structure having a trenched formed in a substrate. A collar oxide is located in an upper portion of the trench and includes a pedestal portion. A method of forming a memory device having a collar oxide with pedestal collar is also disclosed.

Abstract: Disclosed is a method to provide a new deep trench collar process which reduces encroachment of strap diffusion upon array metal oxide semiconductor field effect transistors (MOSFET's) in semiconductor devices. The invention allows a reduced effective deep trench edge bias at the top of the deep trench, without compromising storage capacitance, by maximizing the distance between the MOSFET gate conductor and the deep trench storage capacitor.

Abstract: A semiconductor memory device comprises: a semiconductor substrate; a semiconductor region of a first conductive type formed in the semiconductor substrate; a diffusion region of a second conductive type different from the first conductive type, the diffusion region being formed on the surface of the semiconductor region; a trench formed in the semiconductor substrate so as to be adjacent to the diffusion region; a capacitor insulator film formed on a portion of a side surface of the trench, which extends from a position at a predetermined depth of the trench to a bottom portion of the trench, and on a bottom surface of the trench; a storage node formed so that a surface of the storage node buried in the trench has the same depth as that of the predetermined depth; a first insulator film formed in a portion of the side surface of the trench above the position of the predetermined depth of the trench, the first insulator having a window in a region contacting the diffusion region; and a storage node electrode

Abstract: A laser maintaining and repairing apparatus including a laser oscillator 7, beam guiding apparatus 8 connected to guide a laser beam of the laser oscillator 7, and emitting head 12 for converging the laser beam from the beam guiding apparatus 8 and emitting the beam to a portion to be processed. The beam guiding apparatus 8 includes liquid-tight tubular beam guiding members 9a to 9h. The beam guiding members 9a to 9h are provided with reflecting members 13a, 13b and at least one of mechanisms 10a, 10b and 11a, 11b for providing horizontal turning, horizontal extending, vertical turning and vertical extending operations at the beam guiding members 9a to 9h. With the laser maintaining and repairing apparatus of the noted structure, a laser beam of high energy density can be utilized and processing by the laser beam can be facilitated or the applying range can be increased.

Abstract: The first element separation oxide film consisting of a plurality of line-shaped portions parallel to the bit line is formed on the surface of the P-type silicon substrate. The first and second trenches are formed in that portion of the P-type silicon substrate which is located between an adjacent pair of line-shaped portions of the first element separation oxide film such that both sides of the trenches come in contact with the first element separation oxide film. A sheath plate capacitor is formed in each of the trenches. The second element separation oxide film having a thickness less than that of the first element separation oxide film is formed on that portion of the surface of the P-type silicon substrate which is located between the first and second trenches.

Abstract: This invention is related to a method of manufacturing a semiconductor including a MOSFET.The method comprises a step of forming an opening in a first insulating layer covering a second insulating layer and a surface of semiconductor substrate, so that the second insulating layer covering a gate electrode, and a surface of a source region and a drain region are exposed, a step of burying a conductive material in the opening, and a step of etching the conductive material so that a surface of the second insulating layer is exposed.

Abstract: A gate oxide film is formed on the surface of a P-type silicon substrate. A gate electrode is formed on the gate oxide film. Phosphorus is ion-implanted into the P-type silicon substrate, using the gate electrode as a mask. Thus, N.sup.- -type layers of LDD regions are formed in the P-type silicon substrate. Sidewall regions of material having a high dielectric constant are formed on both sides of the gate electrode. The P-type silicon substrate is etched downward adjacent to both the sidewall regions. N.sup.+ -type layers of source and drain regions are formed in the etched surface of the P-type silicon substrate.

Abstract: An element separating oxide film is formed on a P-type semiconductor substrate by means of a selective oxidation method, and then a gate oxide film is formed on the element separating oxide film by a thermal oxidation method. A gate electrode film made of an N-type polysilicon material is formed so as to extend along a step portion of the element separating oxide film on the semiconductor substrate. The upper surface of the gate electrode film is flattened by means of a surface polishing method. Then, isotropic etching is performed by using a resist pattern as a mask, thereby forming a gate electrode. Since in the method the upper surface of the gate electrode film in the flattened, the semiconductor substrate is prevented from being subject to over-etching when a gage electrode is formed, so that the changes of characteristics of MOS transistors are prevented whose gate insulative films have been becoming thinner as their elements have been finer.

Abstract: The present structure is characterized by the electrode of a trench capacitor of a DRAM and a periphery thereof. A trench is formed adjacent to an N type region in a substrate. An insulating film is formed on the side wall of this trench and only a part of the insulating film around the upper portion of the trench is removed, forming a window. An N type polycrystalline silicon film of a lower capacitor electrode is formed over a region from the bottom of the trench to below the window, and a capacitor insulating film is formed on this polycrystalline silicon film. A polycrystalline silicon film which becomes a first upper capacitor electrode is formed on the capacitor insulating film, filling the trench up to the lower edge of the window. A monocrystalline silicon film which becomes a second upper capacitor electrode is formed on the latter polycrystalline silicon film in such a way as to contact an N type region, filling the upper portion of the trench.

Abstract: The first element separation oxide film consisting of a plurality of line-shaped portions parallel to the bit line is formed on the surface of the P-type silicon substrate. The first and second trenches are formed in that portion of the P-type silicon substrate which is located between an adjacent pair of line-shaped portions of the first element separation oxide film such that both sides of the trenches come in contact with the first element separation oxide film. A sheath plate capacitor is formed in each of the trenches. The second element separation oxide film having a thickness less than that of the first element separation oxide film is formed on that portion of the surface of the P-type silicon substrate which is located between the first and second trenches.

Abstract: An element separating oxide film is formed on a P-type semiconductor substrate by means of a selective oxidation method, and then a gate oxide film is formed on the element separating oxide film by a thermal oxidation method. A gate electrode film made of an N-type polysilicon material is formed so as to extend along a step portion of the element separating oxide film on the semiconductor substrate. The upper surface of the gate electrode film is flattened by means of a surface polishing method. Then, isotropic etching is performed by using a resist pattern as a mask, thereby forming a gate electrode. Since in the method the upper surface of the gate electrode film in the flattened, the semiconductor substrate is prevented from being subject to over-etching when a gage electrode is formed, so that the changes of characteristics of MOS transistors are prevented whose gate insulative films have been becoming thinner as their elements have been finer.

Abstract: A semiconductor body has a first and a second element formation surface. The semiconductor body is constructed in such a manner that a first semiconductor substrate, which has a first main surface at which the plane appears, is laminated to a second semiconductor substrate, which has a second main surface at which the plane appears. Made in the first semiconductor substrate is at least one opening at which the second main surface of the second semiconductor substrate. The first main surface of the first semiconductor substrate becomes the first element formation surface of the semiconductor body, and the second main surface of the second semiconductor substrate becomes the second element formation surface of the body.