Patents by Inventor Akira Uedono

Akira Uedono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9905433
    Abstract: An ion implantation results in defects generated in a nitride semiconductor layer. If the nitride semiconductor layer is set at a particular temperature for a predetermined time period after the ion implantation, the defects may probably be clustering. Provided is a manufacturing method of a semiconductor device including a nitride semiconductor layer comprising: implanting impurities in the nitride semiconductor layer; and increasing a temperature of the nitride semiconductor layer from an initial temperature to a target temperature and annealing the nitride semiconductor layer at the target temperature for a predetermined time period; wherein in the annealing, in at least part of temperature regions below a first temperature between the initial temperature and the target temperature, the nitride semiconductor layer is annealed at a temperature increase speed lower than in a temperature region not lower than the first temperature.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: February 27, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shinya Takashima, Katsunori Ueno, Masaharu Edo, Akira Uedono
  • Publication number: 20180005843
    Abstract: An ion implantation results in defects generated in a nitride semiconductor layer. If the nitride semiconductor layer is set at a particular temperature for a predetermined time period after the ion implantation, the defects may probably be clustering. Provided is a manufacturing method of a semiconductor device including a nitride semiconductor layer comprising: implanting impurities in the nitride semiconductor layer; and increasing a temperature of the nitride semiconductor layer from an initial temperature to a target temperature and annealing the nitride semiconductor layer at the target temperature for a predetermined time period; wherein in the annealing, in at least part of temperature regions below a first temperature between the initial temperature and the target temperature, the nitride semiconductor layer is annealed at a temperature increase speed lower than in a temperature region not lower than the first temperature.
    Type: Application
    Filed: May 31, 2017
    Publication date: January 4, 2018
    Inventors: Shinya TAKASHIMA, Katsunori UENO, Masaharu EDO, Akira UEDONO
  • Patent number: 8058186
    Abstract: A focus ring is shaped by cutting off a silicon carbide body formed by a sintering method or a CVD method. The shaped focus ring is exposed to a plasma generated from at least one of a carbon tetra fluoride gas and an oxygen gas for producing impurities, and the impurities are introduced to void-like defects existing in the vicinity of a surface of the focus ring. Subsequently, positrons are injected in the vicinity of the surface of the focus ring into which the impurities are introduced, and the defect density in the vicinity of the surface of the focus ring is detected by the positron annihilation method.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: November 15, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Tsuyoshi Moriya, Kouji Mitsuhashi, Akira Uedono
  • Publication number: 20060096703
    Abstract: A focus ring is shaped by cutting off a silicon carbide body formed by a sintering method or a CVD method. The shaped focus ring is exposed to a plasma generated from at least one of a carbon tetra fluoride gas and an oxygen gas for producing impurities, and the impurities are introduced to void-like defects existing in the vicinity of a surface of the focus ring. Subsequently, positrons are injected in the vicinity of the surface of the focus ring into which the impurities are introduced, and the defect density in the vicinity of the surface of the focus ring is detected by the positron annihilation method.
    Type: Application
    Filed: November 10, 2005
    Publication date: May 11, 2006
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Tsuyoshi Moriya, Kouji Mitsuhashi, Akira Uedono
  • Patent number: 6919563
    Abstract: Disclosed is a defect evaluation apparatus comprising a source section having a source for generating positrons and a moderator for decelerating the positrons, a sample holding section for holding a sample to be measured, a transfer section for transferring the positrons from the source section to the sample holding section, and detection means for detecting ? rays emitted from the sample being measured, characterized in that the apparatus further comprises heating means for heating the moderator in a position where there is a possibility of the source being thermally damaged if there is no protection means mentioned below in the source section, and protection means for protecting the source from the heating means and heated moderator when the moderator is being heated using the heating means.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: July 19, 2005
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Akira Uedono, Atsushi Ogura
  • Publication number: 20040173745
    Abstract: Disclosed is a defect evaluation apparatus comprising a source section having a source for generating positrons and a moderator for decelerating the positrons, a sample holding section for holding a sample to be measured, a transfer section for transferring the positrons from the source section to the sample holding section, and detection means for detecting &ggr; rays emitted from the sample being measured, characterized in that the apparatus further comprises heating means for heating the moderator in a position where there is a possibility of the source being thermally damaged if there is no protection means mentioned below in the source section, and protection means for protecting the source from the heating means and heated moderator when the moderator is being heated using the heating means.
    Type: Application
    Filed: August 28, 2003
    Publication date: September 9, 2004
    Applicant: SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER
    Inventors: Akira Uedono, Atsushi Ogura