Abstract: [Problem] The present invention has as an object to provide an antiviral agent effective as a remedy for COVID-1 9 and other viral infections. [Resolution Means] Provided is an antiviral agent and the like, made of: the compound represented by general formula (1) or (2) below [R1 being —(CH2)n1—Z1—R11 2 r —CH—(—Z1—R11,)(n1 being 0 or 1; Z1 being a single bond, —O—, —NH—, —S—, —SO—, —SO2—,SO—CO—, —CO—O—, or —CH?N—O—; R11 being a hydrogen atom, an alkyl group having 1 to 6 carbons, —NR12 R13, —N3,—NO2,—CN, —CH2—CO—O—R14, or a five- or six-membered heterocyclic group including a nitrogen atom; R12 and R13 each independently being a hydrogen atom or an alkyl group having 1 to 6 carbons; and R14 being a hydrogen atom or an alkyl group having 1 to 6 carbons], a derivative thereof, a salt of these compounds, or a solvate thereof.

Abstract: A semiconductor device includes first and second semiconductor chips mounted on one package. In the first semiconductor chip, a current generation circuit generates a sense current in accordance with a load current and a fault current indicating that an abnormality detection circuit has detected an abnormality, and allows either one of the currents to flow through a current detecting resistor in accordance with presence or absence of detection of the abnormality. In the second semiconductor chip, a storage circuit stores a current value of the fault current obtained in an inspection process of the semiconductor device as a determination reference value. An arithmetic processing circuit sets a standard range based on the determination reference value, and determines presence or absence of detection of the abnormality based on whether or not a current value indicated by a digital signal of an analog-digital conversion circuit is included within the standard range.

Abstract: A semiconductor integrated power device including: an output transistor configured to drive an external load element; a temperature detection circuit configured to: output a first detection signal in reference to a temperature difference between a temperature of the output transistor and an ambient temperature; and output a second detection signal in reference to a temperature difference between a temperature of the output transistor and a first reference temperature; and a current limiter circuit configured to limit a current flowing through the output transistor according to the first detection signal and the second detection signal. The temperature detection circuit activates and inactivates the first detection signal or the second detection signal based on an output of a first hysteresis circuit.

Abstract: A control method of a semiconductor device includes inspecting an electrical property of a current detection circuit in the first semiconductor chip, writing information on a correction equation obtained on the basis of an inspection result in a memory circuit of the second semiconductor chip, and correcting, with the second semiconductor chip, a detection result obtained by the current detection circuit on the basis of the information on the correction equation.

Abstract: A hot sensor detects a temperature of an output transistor and a cold sensor detects a temperature of a position distant from the output transistor. When the temperature of the hot sensor rises more than a reference temperature, a temperature detecting circuit asserts an overtemperature detecting signal, and when a temperature difference between the hot sensor and the cold sensor is more than a reference temperature difference, the above circuit asserts the temperature difference detecting signal. A current limiting circuit generates a limited current signal sequentially variable with the negative temperature characteristic for the temperature of the cold sensor and controls a drive current of the output transistor to a current value depending on the signal level of the limited current signal when the overtemperature detecting signal is asserted.

Abstract: A sophisticated semiconductor device is provided. A semiconductor device including an IPD chip and an MCU chip which are included in one package. The IPD chip includes: a power transistor that drives an external load; a gate drive circuit that drives the power transistor; and a protection circuit that protects the power transistor from having a breakdown. The MCU chip includes an arithmetic processing unit that performs arithmetic processing based on detected data output from the protection circuit, and a storage unit that stores a program for the arithmetic processing unit. The MCU chip has a function of controlling operation of the power transistor according to the detected data.

Abstract: A control method of a semiconductor device includes inspecting an electrical property of a current detection circuit in the first semiconductor chip, writing information on a correction equation obtained on the basis of an inspection result in a memory circuit of the second semiconductor chip, and correcting, with the second semiconductor chip, a detection result obtained by the current detection circuit on the basis of the information on the correction equation.

Abstract: A semiconductor device with the highly precise current detecting function is provided. Current detection is performed using a semiconductor device in which two semiconductor chips are mounted in one package. The first semiconductor chip is provided with an electric power supply transistor to supply power to a load via a load driving terminal, and a current detection circuit to detect a current flowing through the load driving terminal. In the inspection process of the semiconductor device, the electrical property of the current detection circuit in the first semiconductor chip is inspected, and the information on a correction equation obtained as the inspection result is written in a memory circuit of the second semiconductor chip. The second semiconductor chip corrects the detection result obtained by the current detection circuit based on the information on the correction equation written in the memory circuit concerned.

Abstract: A semiconductor integrated power device including: an output transistor configured to drive an external load element; a temperature detection circuit configured to: output a first detection signal in reference to a temperature difference between a temperature of the output transistor and an ambient temperature; and output a second detection signal in reference to a temperature difference between a temperature of the output transistor and a first reference temperature; and a current limiter circuit configured to limit a current flowing through the output transistor according to the first detection signal and the second detection signal. The temperature detection circuit activates and inactivates the first detection signal or the second detection signal based on an output of a first hysteresis circuit.

Abstract: A semiconductor device includes first and second semiconductor chips mounted on one package. In the first semiconductor chip, a current generation circuit generates a sense current in accordance with a load current and a fault current indicating that an abnormality detection circuit has detected an abnormality, and allows either one of the currents to flow through a current detecting resistor in accordance with presence or absence of detection of the abnormality. In the second semiconductor chip, a storage circuit stores a current value of the fault current obtained in an inspection process of the semiconductor device as a determination reference value. An arithmetic processing circuit sets a standard range based on the determination reference value, and determines presence or absence of detection of the abnormality based on whether or not a current value indicated by a digital signal of an analog-digital conversion circuit is included within the standard range.

Abstract: A load driving device 10 includes a temperature detector TD1 that sets a temperature difference detection signal dt_ot to active when a temperature difference Tdif between a temperature Ttr of an output transistor T1 and an ambient temperature becomes more than a reference temperature difference Tdref1, and sets an over temperature detection signal at_ot to active when the temperature Ttr of the output transistor T1 becomes higher than a reference temperature Tref1, a current limiter IL1 that limits a GS current of the output transistor T1 when any one of the detection signals becomes active, and the output transistor T1 that turns off regardless of an external input signal IN when any one of the detection signals becomes active.

Abstract: A semiconductor device includes first and second semiconductor chips, a plurality of leads, a plurality of wires, and a sealing body sealing those components. A first pad electrode, a second pad electrode, and an internal wiring electrically connected to the first and second electrode pads are formed on a main surface of the first semiconductor chip. A third pad electrode of the second semiconductor chip is electrically connected to the first electrode pad of the first semiconductor chip via a first wire, and the second electrode pad of the first semiconductor chip is electrically connected to a first lead via a second wire. A distance between the first lead and the first semiconductor chip is smaller than a distance between the first lead and the second semiconductor chip. The first electrode pad, the second electrode pad and the internal wiring are not connected to any circuit formed in the first semiconductor chip.

Abstract: A sophisticated semiconductor device is provided. A semiconductor device including an IPD chip and an MCU chip which are included in one package. The IPD chip includes: a power transistor that drives an external load; a gate drive circuit that drives the power transistor; and a protection circuit that protects the power transistor from having a breakdown. The MCU chip includes an arithmetic processing unit that performs arithmetic processing based on detected data output from the protection circuit, and a storage unit that stores a program for the arithmetic processing unit. The MCU chip has a function of controlling operation of the power transistor according to the detected data.

Abstract: A semiconductor device with the highly precise current detecting function is provided. Current detection is performed using a semiconductor device in which two semiconductor chips are mounted in one package. The first semiconductor chip is provided with an electric power supply transistor to supply power to a load via a load driving terminal, and a current detection circuit to detect a current flowing through the load driving terminal. In the inspection process of the semiconductor device, the electrical property of the current detection circuit in the first semiconductor chip is inspected, and the information on a correction equation obtained as the inspection result is written in a memory circuit of the second semiconductor chip. The second semiconductor chip corrects the detection result obtained by the current detection circuit based on the information on the correction equation written in the memory circuit concerned.

Abstract: A load driving device 10 includes a temperature detector TD1 that sets a temperature difference detection signal dt_ot to active when a temperature difference Tdif between a temperature Ttr of an output transistor T1 and an ambient temperature becomes more than a reference temperature difference Tdref1, and sets an over temperature detection signal at_ot to active when the temperature Ttr of the output transistor T1 becomes higher than a reference temperature Tref1, a current limiter IL1 that limits a GS current of the output transistor T1 when any one of the detection signals becomes active, and the output transistor T1 that turns off regardless of an external input signal IN when any one of the detection signals becomes active.

Abstract: A semiconductor device includes first and second semiconductor chips, a plurality of leads, a plurality of wires, and a sealing body sealing those components. A first pad electrode, a second pad electrode, and an internal wiring electrically connected to the first and second electrode pads are formed on a main surface of the first semiconductor chip. A third pad electrode of the second semiconductor chip is electrically connected to the first electrode pad of the first semiconductor chip via a first wire, and the second electrode pad of the first semiconductor chip is electrically connected to a first lead via a second wire. A distance between the first lead and the first semiconductor chip is smaller than a distance between the first lead and the second semiconductor chip. The first electrode pad, the second electrode pad and the internal wiring are not connected to any circuit formed in the first semiconductor chip.

Abstract: A CCD image sensor includes a photo-diode region segmented by an element separation region; and a CCD register connected with the photo-diode region through a transfer gate. The photo-diode region includes a plurality of tapered portions, and each of the plurality of tapered portions is formed to become wider in a direction of the transfer gate.

Abstract: A solid-state imaging device includes a light receiving section (LRS) comprising pixels. The LRS is divided into division regions; a charge transferring section (CTS) transferring charges accumulated in the LRS; an accumulation control electrode provided between the LRS and the CTS transfers charge accumulated in the LRS to the CTS responsive to an accumulation control signal; a monitoring sensor group comprising monitoring sensors respectively provided for the division regions, outputting sensor outputs of the monitoring sensors corresponding to charges amounts of the division regions; a charge detecting circuit outputting a charge detection signal indicating that a predetermined charge quantity is accumulated in at least one of the division regions, based on the sensor outputs from the monitoring sensor group; and a signal control circuit outputting the accumulation control signal in response to the charge detection signal.

Abstract: A CCD image sensor includes a photo-diode region segmented by an element separation region; and a CCD register connected with the photo-diode region through a transfer gate. The photo-diode region includes a plurality of tapered portions, and each of the plurality of tapered portions is formed to become wider in a direction of the transfer gate.

Abstract: A solid-state imaging apparatus includes a pixel array comprising a plurality of light receiving elements disposed in a charge transfer direction, the plurality of light receiving elements converting a light signal into an electric signal, a first charge transfer unit and a second charge transfer unit arranged on each side of the pixel array and transferring a signal charge input from the pixel array in the charge transfer direction, a first floating diffusion region connected to the first charge transfer unit, a second floating diffusion region connected to the second charge transfer unit, a wiring layer connecting the first floating diffusion region with the second floating diffusion region, and an output circuit connected to the wiring layer and output a signal voltage in accordance with a potential of the first floating diffusion region and the second floating diffusion region.