Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.

Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.

Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.

Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.

Abstract: A semiconductor storage device according to an embodiment includes multiple memory cells which electrically rewrite data, a well control circuit which outputs an erasure voltage to be applied to a well through an output terminal, a first pump circuit which outputs a voltage set by boosting an input voltage to the output terminal, a second pump circuit which outputs a voltage set by boosting the input voltage to the output terminal and outputs a voltage higher than an output voltage of the first pump circuit, a pump switching detecting circuit which outputs an assist signal to perform a boosting operation on at least one of the first pump circuit and the second pump circuit and an erase pulse control circuit which sets target voltages of the first pump circuit and the second pump circuit, on the basis of setting values to set a target voltage of the erasure voltage.

Abstract: According to one embodiment, a nonvolatile semiconductor storage device includes a first well region of a first conductivity type, a second well region of the first conductivity type, a third well region of a second conductivity type, a bit line and a column decoder. A first cell array including a plurality of memory cells is formed in the first well region. A second cell array including a plurality of memory cells is formed in the second well region. The third well region includes the first and second well regions. The bit line is connected to the memory cells included in the first cell array and the memory cells included in the second cell array. The column decoder is connected to the bit line.

Abstract: A nonvolatile semiconductor storage device includes a memory cell array including a plurality of memory cells arranged at intersection positions of word lines and bit lines in a matrix form, and a row decoder including a row sub-decoder to which a lower address for selecting a word line is input, wherein one unit of the row sub-decoder for selecting one word line is constituted of a first transistor of a first conduction type, and a second transistor of a second conduction type, and a gate electrode of each of the first and second transistors is arranged in a direction in which the bit lines are arranged.

Abstract: A power circuit includes a reference potential circuit, a step-up circuit, and a conversion circuit. The reference potential circuit generates a reference potential. The step-up circuit generates a desired internal potential by stepping up a power supply potential. The step-up circuit includes a comparison circuit, a differential amplifier circuit, and a switch element. The comparison circuit outputs the result of comparison between a potential and the reference potential. The differential amplifier circuit is turned on or off by the operation control signal. The switch element performs on/off control according to the operation control signal and resets the output potential of the differential amplifier circuit. The conversion circuit converts the of the operation control signal so as to make longer the on period of the differential amplifier circuit and the off period of switch element.

Abstract: A nonvolatile semiconductor memory device includes a multi-layer insulating film having at least charge storage layers and formed on bottom surfaces and both side surfaces of a plurality of trench portions respectively formed in portions between the plurality of active areas formed in a first direction, a plurality of gate electrodes filled in internal portions of the plurality of trench portions with the multi-layer insulating film, a plurality of first metal interconnections formed in a second direction and each functioning as a bit line or source line, and a plurality of first conductivity-type diffusion layer regions arranged in a staggered form in corresponding portions of the plurality of active areas which intersect with the plurality of first metal interconnections. The device further includes a plurality of connection contacts form to respectively connect the plurality of first conductivity-type diffusion layer regions to the plurality of first metal interconnections.

Abstract: A semiconductor storage device according to an embodiment includes a plurality of memory cells which electrically rewrite data by controlling the amount of charges accumulated in a floating gate formed on a well through a tunnel insulating film. The semiconductor storage device includes a well control circuit which outputs an erasure voltage to be applied to the well through an output terminal. The semiconductor storage device includes a first pump circuit which outputs a voltage set by boosting an input voltage to the output terminal. The semiconductor storage device includes a second pump circuit which outputs a voltage set by boosting the input voltage to the output terminal and outputs a voltage higher than an output voltage of the first pump circuit. The semiconductor storage device includes a pump switching detecting circuit which outputs an assist signal to perform a boosting operation on at least one of the first pump circuit and the second pump circuit.

Abstract: According to one embodiment, a nonvolatile semiconductor storage device includes a first well region of a first conductivity type, a second well region of the first conductivity type, a third well region of a second conductivity type, a bit line and a column decoder. A first cell array including a plurality of memory cells is formed in the first well region. A second cell array including a plurality of memory cells is formed in the second well region. The third well region includes the first and second well regions. The bit line is connected to the memory cells included in the first cell array and the memory cells included in the second cell array. The column decoder is connected to the bit line.

Abstract: A power circuit includes a reference potential circuit, a step-up circuit, and a conversion circuit. The reference potential circuit generates a reference potential. The step-up circuit generates a desired internal potential by stepping up a power supply potential. The step-up circuit includes a comparison circuit, a differential amplifier circuit, and a switch element. The comparison circuit outputs the result of comparison between a potential and the reference potential. The differential amplifier circuit is turned on or off by the operation control signal. The switch element performs on/off control according to the operation control signal and resets the output potential of the differential amplifier circuit. The conversion circuit converts the of the operation control signal so as to make longer the on period of the differential amplifier circuit and the off period of switch element.

Abstract: A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first inter-gate insulating film. The second memory has a third select transistor and a second memory cell transistor. The second memory cell transistor has a second floating gate on a second gate insulating film and a second control gate on a second inter-gate insulating film. The first and second gate insulating films have the same film thickness. The first and second floating gates have the same film thickness. The first and second inter-gate insulating films have the same film thickness. The first and second control gates have the same film thickness.

Abstract: A nonvolatile semiconductor memory device includes a multi-layer insulating film having at least charge storage layers and formed on bottom surfaces and both side surfaces of a plurality of trench portions respectively formed in portions between the plurality of active areas formed in a first direction, a plurality of gate electrodes filled in internal portions of the plurality of trench portions with the multi-layer insulating film, a plurality of first metal interconnections formed in a second direction and each functioning as a bit line or source line, and a plurality of first conductivity-type diffusion layer regions arranged in a staggered form in corresponding portions of the plurality of active areas which intersect with the plurality of first metal interconnections. The device further includes a plurality of connection contacts form to respectively connect the plurality of first conductivity-type diffusion layer regions to the plurality of first metal interconnections.

Abstract: A nonvolatile semiconductor storage device includes a memory cell array including a plurality of memory cells arranged at intersection positions of word lines and bit lines in a matrix form, and a row decoder including a row sub-decoder to which a lower address for selecting a word line is input, wherein one unit of the row sub-decoder for selecting one word line is constituted of a first transistor of a first conduction type, and a second transistor of a second conduction type, and a gate electrode of each of the first and second transistors is arranged in a direction in which the bit lines are arranged.

Abstract: The local row decoder includes a first MOS transistor of a first conductivity type having one end connected to the local word line, the other end supplied with a first voltage, and a gate connected to the global word line, and a second MOS transistor of a second conductivity type having one end connected to the local word line, the other end supplied with a second voltage, and a gate connected to the global word line. The global row decoder is capable of independently selecting either a first global word line or a second global word line. The first global word line is connected to the first MOS transistor and the second MOS transistor both connected to any one of the local word lines. The second global word line is connected to the first MOS transistor and the second MOS transistor both connected to another adjacent local word line.

Abstract: A semiconductor memory device includes a memory cell array, first bit lines, second bit lines, a first precharge circuit, a sense amplifier, and a read control circuit. The memory cell array has a first cell array including first memory cells arranged in a matrix and a second cell array including second memory cells. The first bit line electrically connects the first memory cells in a same column. The second bit line electrically connects the second memory cells in a same column. The first precharge circuit precharges the first bit lines in a read operation. The sense amplifier amplifies the data read from the first memory cells in a read operation. The read control circuit precharges and discharges the second bit lines in a read operation and, on the basis of the time required to precharge and discharge the second bit lines, controls the first precharge circuit and the sense amplifier.

Abstract: A semiconductor memory device comprises a first to a fourth semiconductor layer of a first conductivity type which are formed in a fifth semiconductor layer of a second conductivity type in such a manner that they are isolated from one another, memory cells each of which includes a first MOS transistor formed on the first semiconductor layer, a second and a third MOS transistor which are formed on the second and third semiconductor layers, respectively, a first metal wiring layer which connects the gate of the first MOS transistor to the source or drain of at least one of the second and third MOS transistors, and a first contact plug which connects the fourth semiconductor layer to the first metal wiring layer. The first wiring layer is in the lowest layer of the metal wiring lines connected to the gate of the first MOS transistor.

Abstract: A semiconductor memory device includes a memory cell array, word lines, and a row decoder. The memory cell array includes memory cells arranged in a matrix. The memory cell includes a first MOS transistor having a charge accumulation layer and a control gate and a second MOS transistor. The word line connects the control gates of the first MOS transistors. The row decoder includes a first address decode circuit, a second address decode circuit, and a transfer gate. The first address decode circuit decodes m bits in a n-bit row address signal (m and n are a natural number satisfying the expression m<n). The second address decode circuit decodes (n?m) bits in the row address signal. The transfer gate supplies the output of the first address decode circuit to the word line according to the output of the second address decoded circuit.

Abstract: The present invention relates to a labeling enzyme and a method of detecting and/or quantifying a target substance using this labeling enzyme. The present invention provides a labeling enzyme that catalyzes a reaction of gelling a substrate. By measuring changes in physical properties such as the film thickness and/or refractive index of a film produced by the gelling reaction catalyzed by the labeling enzyme of the present invention, it is possible to quickly and highly sensitively detect and/or quantify a target substance while minimizing the effects of coexisting substances.