Patents by Inventor Akiteru Rai

Akiteru Rai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8344486
    Abstract: In a COF of an embodiment of the present invention, the smaller distance to edges of a heat-releasing member an area of the heat-releasing member has, the larger openings the area has. Accordingly, a volume per area (an area per length) of the heat-releasing member decreases toward the edges. The arrangement improves flexibility of the COF. This prevents a stress caused by bending the COF from concentrating at the edges. This makes it possible to prevent a line on an insulating film from being broken. Also, it becomes possible to prevent an anisotropic conductive resin from coming off which is used to bond the COF with a display panel in providing the COF in a display apparatus.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: January 1, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tomokatsu Nakagawa, Yasunori Chikawa, Akiteru Rai, Tatsuya Katoh, Takuya Sugiyama
  • Publication number: 20110108979
    Abstract: In a COF of an embodiment of the present invention, the smaller distance to edges of a heat-releasing member an area of the heat-releasing member has, the larger openings the area has. Accordingly, a volume per area (an area per length) of the heat-releasing member decreases toward the edges. The arrangement improves flexibility of the COF. This prevents a stress caused by bending the COF from concentrating at the edges. This makes it possible to prevent a line on an insulating film from being broken. Also, it becomes possible to prevent an anisotropic conductive resin from coming off which is used to bond the COF with a display panel in providing the COF in a display apparatus.
    Type: Application
    Filed: July 7, 2009
    Publication date: May 12, 2011
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Tomokatsu Nakagawa, Yasunori Chikawa, Akiteru Rai, Tatsuya Katoh, Takuya Sugiyama
  • Patent number: 7470998
    Abstract: The present invention relates to a semiconductor device in which an electrode of a device formed on a substrate such as a semiconductor wafer and an electrode of a wiring structure such as an interposer are connected to each other through a connecting electrode extending through the substrate, and a method of manufacturing the same. A semiconductor device according to the present invention comprises a first substrate including a front surface and a back surface, a first device having a first electrode being formed on the front surface; and a wiring structure formed with a second electrode, the wiring structure having a principal surface. The first electrode of the first device and the second electrode of the wiring structure are connected to each other by a connecting electrode extending through the first substrate from the front surface to the back surface thereof. Substantially all the back surface of the first substrate is bonded to the principal surface of the wiring structure.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: December 30, 2008
    Assignees: Octec Inc., Tokyo Electron Limited, Sharp Kabushiki Kaisha, Ibiden Co., Ltd.
    Inventors: Katsuya Okumura, Koji Maruyama, Kazuya Nagaseki, Akiteru Rai
  • Patent number: 7084005
    Abstract: The present invention relates to a semiconductor device in which an electrode of a device formed on a substrate such as a semiconductor wafer and an electrode of a wiring structure such as an interposer are connected to each other through a connecting electrode extending through the substrate, and a method of manufacturing the same. A semiconductor device according to the present invention includes a first substrate including a front surface and a back surface, a first device having a first electrode being formed on the front surface; and a wiring structure formed with a second electrode, the wiring structure having a principal surface. The first electrode of the first device and the second electrode of the wiring structure are connected to each other by a connecting electrode extending through the first substrate from the front surface to the back surface thereof. Substantially all the back surface of the first substrate is bonded to the principal surface of the wiring structure.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: August 1, 2006
    Assignees: Octec Inc., Tokyo Electron Limited, Sharp Kabushiki Kaisha, Ibiden Co., Ltd.
    Inventors: Katsuya Okumura, Koji Maruyama, Kazuya Nagaseki, Akiteru Rai
  • Publication number: 20060154473
    Abstract: The present invention relates to a semiconductor device in which an electrode of a device formed on a substrate such as a semiconductor wafer and an electrode of a wiring structure such as an interposer are connected to each other through a connecting electrode extending through the substrate, and a method of manufacturing the same. A semiconductor device according to the present invention comprises a first substrate including a front surface and a back surface, a first device having a first electrode being formed on the front surface; and a wiring structure formed with a second electrode, the wiring structure having a principal surface. The first electrode of the first device and the second electrode of the wiring structure are connected to each other by a connecting electrode extending through the first substrate from the front surface to the back surface thereof. Substantially all the back surface of the first substrate is bonded to the principal surface of the wiring structure.
    Type: Application
    Filed: March 13, 2006
    Publication date: July 13, 2006
    Inventors: Katsuya Okumura, Koji Maruyama, Kazuyu Nagaseki, Akiteru Rai
  • Publication number: 20050087853
    Abstract: The present invention relates to a semiconductor device in which an electrode of a device formed on a substrate such as a semiconductor wafer and an electrode of a wiring structure such as an interposer are connected to each other through a connecting electrode extending through the substrate, and a method of manufacturing the same. A semiconductor device according to the present invention comprises a first substrate including a front surface and a back surface, a first device having a first electrode being formed on the front surface; and a wiring structure formed with a second electrode, the wiring structure having a principal surface. The first electrode of the first device and the second electrode of the wiring structure are connected to each other by a connecting electrode extending through the first substrate from the front surface to the back surface thereof. Substantially all the back surface of the first substrate is bonded to the principal surface of the wiring structure.
    Type: Application
    Filed: May 28, 2004
    Publication date: April 28, 2005
    Inventors: Katsuya Okumura, Koji Maruyama, Kazuya Nagaseki, Akiteru Rai
  • Patent number: 5447886
    Abstract: In mounting a semiconductor chip on a circuit board by a flip chip bonding method, an improved mounting method holds the circuit with a warp prevention device, on which the semiconductor chip is placed, while the circuit board is treated with heat for the reflow of the solder bumps. As a result, the circuit board is prevented from warping when heated at a temperature at which the solder bumps melt.
    Type: Grant
    Filed: February 4, 1994
    Date of Patent: September 5, 1995
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Akiteru Rai
  • Patent number: 5397864
    Abstract: A wiring board including a plate; at least one conductive strip provided on the plate, the conductive strip having a specified connection position; and an electrically insulating film covering the conductive strip and having a slit extending in a direction crossing the longitudinal direction of the conductive strip. A tip of the conductive strip in the vicinity of the connection position has a distance from the connection position in a longitudinal direction of the conductive strip. The slit is formed at a position corresponding to the connection position.
    Type: Grant
    Filed: November 18, 1992
    Date of Patent: March 14, 1995
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akiteru Rai, Keiji Yamamura
  • Patent number: 4818728
    Abstract: A method for making a semiconductor device of a type comprising at least first and second semiconductor circuit units, which method comprises the step of forming a plurality of connecting electrodes on an upper surface of each of at least first and second semiconductor substrates; forming an electrically insulating layer entirely over the upper surface of each of the first and second substrates so as to cover the respective connecting electrodes; partially removing the insulating layer on each of the first and second substrates to permit the respective electrodes to be exposed to the outside; forming metal studs on the first substrate in contact with the electrodes so as to protrude outwardly of the respective insulating layer to complete the first semiconductor unit and forming solder deposits on the second substrate in contact with the respective electrodes on such second substrate to complete the second semiconductor unit; combining the first and second semiconductor units with the metal studs in the first
    Type: Grant
    Filed: December 3, 1987
    Date of Patent: April 4, 1989
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Akiteru Rai, Keiji Yamamura, Takashi Nukii
  • Patent number: 4766085
    Abstract: A method for manufacturing a contact type one-dimensional image sensor, which includes the step of providing a light receiving element portion composed of one or more of Group II-VI compounds semiconductor containing Cd on a substrate, and also providing a matrix wiring portion on the same substrate as that of the light receiving element portion, and the method is characterized by the step of forming an insulating layer for the formation of the matrix wiring portion in such a manner as to cover the light receiving element portion.
    Type: Grant
    Filed: August 7, 1986
    Date of Patent: August 23, 1988
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Satoshi Nishigaki, Ryusuke Kita, Shuhei Tsuchimoto, Akiteru Rai, Masaru Iwasaki, Yuzi Matsuda, Takashi Nukii