Patents by Inventor Akitsugu Murauchi

Akitsugu Murauchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4754270
    Abstract: A displaying apparatus using a raster scanning type display such as a CRT, wherein vertical and horizontal positions are addressed respectively by an address counter for displaying an image stored in a character memory containing a matrix of horizontal and vertical dot information. Start address data, for locating the position of the image on the display, is loaded into vertical address and horizontal address counters which are then incremented by a carry output from horizontal and vertical adders respectively associated with the horizontal and vertical counters. The adder for the vertical address counter repeats adding operations according to predetermined addend data four times in one horizontal blanking period and twice in one vertical blanking period. The adder for the horizontal address counter repeats adding operations according to predetermined addend data at intervals selected to be a fraction, e.g. 1/4th, the usual horizontal dot interval.
    Type: Grant
    Filed: February 12, 1985
    Date of Patent: June 28, 1988
    Assignee: Nintendo Co., Ltd.
    Inventor: Akitsugu Murauchi
  • Patent number: 4521020
    Abstract: A cathode ray tube is coupled to an electric circuit to display characters on the screen thereof through horizontal scanning and vertical scanning. A plurality of characters are displayed in one character group comprising characters arranged in rows and columns. A dispaly signal for displaying such characters is obtained from a random-access memory, which comprises a plurality of storing regions having addresses corresponding to the characters arranged in rows and columns forming a character group. When characters are to be displayed the logic one is loaded in the storing regions of the corresponding address, and when the characters are not to be displayed the logic zero is loaded in the storing regions in the corresponding address. The horizontal address of the random-access memory is determined by a counting operation for performing horizontal scanning, while the vertical address of the random-access memory is determined by a counting operation for performing vertical scanning.
    Type: Grant
    Filed: December 9, 1982
    Date of Patent: June 4, 1985
    Assignee: Nintendo Co., Ltd.
    Inventors: Masayuki Uemura, Akitsugu Murauchi, Takehiro Izushi