Abstract: An output circuit includes: a first input transistor that is provided between a first power supply line and a first intermediate node; a second input transistor that is provided between a second intermediate node and a second power supply line; a first cascode transistor that is provided between the first intermediate node and an output node, and receives a first clip voltage from a first voltage generation circuit; a second cascode transistor that is provided between the output node and the second intermediate node, and receives a second clip voltage from a second voltage generation circuit; a first switch transistor that is provided between the first intermediate node and a gate of the first cascode transistor, and turns on during power down; and a second switch transistor that is provided between the second intermediate node and a gate of the second cascode transistor, and turns on during power down.

Abstract: An output circuit includes: a first input transistor that is provided between a first power supply line and a first intermediate node; a second input transistor that is provided between a second intermediate node and a second power supply line; a first cascode transistor that is provided between the first intermediate node and an output node, and receives a first clip voltage from a first voltage generation circuit; a second cascode transistor that is provided between the output node and the second intermediate node, and receives a second clip voltage from a second voltage generation circuit; a first switch transistor that is provided between the first intermediate node and a gate of the first cascode transistor, and turns on during power down; and a second switch transistor that is provided between the second intermediate node and a gate of the second cascode transistor, and turns on during power down.

Abstract: An output circuit includes first to fourth transistors, first and second constant current units, and a differential pair. The gates of the first and second transistors are supplied with two input signals, respectively. The drain of the first transistor is coupled to the drain of the third transistor and the gate of the fourth transistor. The drain of the second transistor is coupled to the gate of the third transistor and the drain of the fourth transistor. The first constant current unit is coupled to the sources of the third and fourth transistors. The differential pair includes two transistors, and the gates of the two transistors are coupled to the drains of the first and second transistors, respectively. The second constant current unit is coupled to the sources of the two transistors. Two output signals are output from two nodes respectively corresponding to the drains of the two transistors.

Abstract: An output circuit includes first to fourth transistors, first and second constant current units, and a differential pain The gates of the first and second transistors are supplied with two input signals, respectively. The drain of the first transistor is coupled to the drain of the third transistor and the gate of the fourth transistor. The drain of the second transistor is coupled to the gate of the third transistor and the drain of the fourth transistor. The first constant current unit is coupled to the sources of the third and fourth transistors. The differential pair includes two transistors, and the gates of the two transistors are coupled to the drains of the first and second transistors, respectively. The second constant current unit is coupled to the sources of the two transistors. Two output signals are output from two nodes respectively corresponding to the drains of the two transistors.

Abstract: A differential amplifier of the present invention comprises transistors where to each of which one of two inputs to said differential amplifier is provided; current mirror circuits where each of which delivers one of the outputs of the differential amplifier to the load side; and cut-off prevention units where each of which is connected to the connecting point of a transistor to which a monitor current of one of the current mirror circuits flows, and one of the transistors to which the inputs are provided, and applies a current for preventing cutting off the transistor to which the monitor current flows, when the input to the transistor to which the input is provided is L.

Abstract: A differential amplifier of the present invention comprises transistors where to each of which one of two inputs to said differential amplifier is provided; current mirror circuits where each of which delivers one of the outputs of the differential amplifier to the load side; and cut-off prevention units where each of which is connected to the connecting point of a transistor to which a monitor current of one of the current mirror circuits flows, and one of the transistors to which the inputs are provided, and applies a current for preventing cutting off the transistor to which the monitor current flows, when the input to the transistor to which the input is provided is L.

Abstract: A differential amplifier for amplifying an input signal at a constant amplification rate regardless of fluctuation in the center voltage of the input signal. The differential amplifier includes a first differential pair operated when a complementary input signal is greater than or equal to an intermediate level between power supplies. A second differential pair is operated when the complementary input signal is less than or equal to an intermediate level of the power supplies. A current synthesizing circuit synthesizes output currents of the first and second differential pairs to generate output voltage. An output current offset circuit offsets a current corresponding to the output current of one of the differential pairs based on the complementary input signal so that the output voltage becomes the output current of one of the first and second differential pairs.

Abstract: The differential amplifier of the present invention has a current source connected between a grounding wire and a terminal which can be the output point of the differential amplifier among the terminals of each transistor which constitutes the differential amplifier and to which one of two inputs to the differential amplifier is given, or a circuit element connected between the terminals which can be the output points of the differential amplifier, or two transistors which are connected to each of the terminals which can be the output points of the differential amplifier and one of which turns off when the other is on, and one of which turns on when the other is off, and the current source is connected between the two transistors and the grounding wire.

Abstract: A differential amplifier for amplifying an input signal at a constant amplification rate regardless of fluctuation in the center voltage of the input signal. The differential amplifier includes a first differential pair operated when a complementary input signal is greater than or equal to an intermediate level between power supplies. A second differential pair is operated when the complementary input signal is less than or equal to an intermediate level of the power supplies. A current synthesizing circuit synthesizes output currents of the first and second differential pairs to generate output voltage. An output current offset circuit offsets a current corresponding to the output current of one of the differential pairs based on the complementary input signal so that the output voltage becomes the output current of one of the first and second differential pairs.