Abstract: In a method of compiling, the contents of registers corresponding to data arrays having the same array names but having different indexes in sequence with the progress of a loop prior to loop return are moved, and only that having the smallest index among those which should be stored is stored. In this manner, the number of Load/Stores is reduced. Moreover, by unrolling loops, register moves may be omitted. Thus, by the application of the method of register allocation and changing the method of register allocation, execution of loops containing calculations of data arrays is speeded up by the extent of unnecessary memory accesses which have been eliminated.

Abstract: In an image clustering apparatus for classifying an image into plural clusters, modification of cluster parameter is executed by parallel processing as well as parallel processing of comparison of likelihood.

Abstract: In a multiprocessor system in which a master processor and a plurality of slave processors access in common a page mode memory, each slave processor functions such that upon completion of a memory access by the slave processor, the page address which was being accessed prior to that access by the slave processor is reloaded into the page buffer of the memory. Since in general each access by a slave processor is preceded by and followed by an access by the master processor, generally to the same page of the memory, this reduces the number of long accesses that must be executed by the master processor as a result of intervening accesses by slave processors.

Abstract: A multiprocessor system having at least two processing elements, each of which includes a processor and a storage resource, connected via a network, each processor comprising: a task generation device for generating a task which includes information concerning access frequency to the storage resource on each processing element; a predicted termination time collection device for collecting predicted termination time from any processing element, the predicted termination time being time to terminate execution of at least one task assigned to the processing element; an estimated access time storage device for storing time estimated for accessing the storage resource on the processing element and time estimated for accessing the storage resource on any processing element via the network; a processing element determination device for determining which of the processing elements should execute the generated task based on the predicted termination time, the information concerning access frequency and the access time

Abstract: Syntax of a source program is analyzed to translate the source program into an intermediate language. The intermediate language is subjected to optimization to be translated into an object program. A description of macro portions is expressed by a list structure. The macro portions are subjected to a code movement by the optimization. A description of details of the macro portions is expressed by an array. The array corresponding to the description of the details of the macro portions is designated by pointers provided in attributes of elements representing the macro portions in the list structure.

Abstract: Input FIFO buffers serve to store sorted data. A number of the input FIFO buffers equals a first predetermined number N equal to 2.sup.n where n denotes a second predetermined number. A number of comparators equals the second predetermined number n. Intermediate FIFO buffers each have a capacity corresponding to at least two words. A number of the intermediate FIFO buffers equals the first predetermined number N minus 2. Identification numbers (i,j) are assigned to the intermediate FIFO buffers respectively wherein i=1, n-1 and where j=1, 2.sup.(n-1). A first of the comparators outputs a merge result of an i-th of the input FIFO buffers and an (i+N/2)-th of the input FIFO buffers to a (1,i)-th of the intermediate FIFO buffers where i=1, N/2. A j-th of the comparators outputs a merge result of a (j-1,i)-th of the intermediate FIFO buffers and a (j-1,i+2.sup.(n-i) -th of the intermediate FIFO buffers to a (j,i)-th of the intermediate FIFO buffers where j=2, n-1 and where i=1, 2.sup.(n-i).

Abstract: A multiprocessor system is formed of a total of R.sup.n digital processors connected for mutual communication by unidirectional data lines. Each processor is connected for sending data to R other processors, and designating the address of an arbitrary processor as (P.sub.1 P.sub.2, . . . P.sub.i, . . . P.sub.n), the addresses of respective ones of these R processors are determined by executing a one digit right shift (or left shift) of that arbitrary processor address and changing a specific digit P.sub.i of that address to each of a set of values extending from 0 to (R-1).