Abstract: Provided are an apparatus, system and method for offloading data transfer operations between source and destination storage devices to a hardware accelerator. The hardware accelerator includes a memory space and control logic to receive, from a host processor, a command descriptor indicating at least one source storage device having transfer data to transfer to at least one destination storage device and a computational task to perform on the transfer data. The control logic sends read commands to the at least one source storage device to read the transfer data to at least one read buffer in the memory space and performs the computational task on the transfer data to produce modified transfer data. The control logic writes the modified transfer data to at least one write buffer in the memory space to cause the modified transfer data to be written to the at least one destination storage device.

Abstract: Provided are an apparatus, system and method for offloading data transfer operations between source and destination storage devices to a hardware accelerator. The hardware accelerator includes a memory space and control logic to receive, from a host processor, a command descriptor indicating at least one source storage device having transfer data to transfer to at least one destination storage device and a computational task to perform on the transfer data. The control logic sends read commands to the at least one source storage device to read the transfer data to at least one read buffer in the memory space and performs the computational task on the transfer data to produce modified transfer data. The control logic writes the modified transfer data to at least one write buffer in the memory space to cause the modified transfer data to be written to the at least one destination storage device.

Abstract: Provided are an apparatus, system and method for offloading data transfer operations between source and destination storage devices to a hardware accelerator. The hardware accelerator includes a memory space and control logic to receive, from a host processor, a command descriptor indicating at least one source storage device having transfer data to transfer to at least one destination storage device and a computational task to perform on the transfer data. The control logic sends read commands to the at least one source storage device to read the transfer data to at least one read buffer in the memory space and performs the computational task on the transfer data to produce modified transfer data. The control logic writes the modified transfer data to at least one write buffer in the memory space to cause the modified transfer data to be written to the at least one destination storage device.

Abstract: Provided are an apparatus, system and method for offloading data transfer operations between source and destination storage devices to a hardware accelerator. The hardware accelerator includes a memory space and control logic to receive, from a host processor, a command descriptor indicating at least one source storage device having transfer data to transfer to at least one destination storage device and a computational task to perform on the transfer data. The control logic sends read commands to the at least one source storage device to read the transfer data to at least one read buffer in the memory space and performs the computational task on the transfer data to produce modified transfer data. The control logic writes the modified transfer data to at least one write buffer in the memory space to cause the modified transfer data to be written to the at least one destination storage device.

Abstract: An interconnect switch is provided including switching logic executable to facilitate a Peripheral Component Interconnect Express (PCIe)-based interconnect, and further including a control host embedded in the switch to provide one or more enhanced routing capabilities. The control host includes a processor device, memory, and software executable by the processor device to process traffic received at one or more ports of the switch to redirect at least a portion of the traffic to provide the one or more enhanced routing capabilities.

Abstract: A device to process data packets for communication across PHY layers which are of different respective communication protocols. In an embodiment, the device includes a first protocol stack and a second protocol stack which are each for a PCIe™ communication protocol. The first protocol stack and a second protocol stack may interface, respectively, with a first physical (PHY) layer and a second PHY layer of the device. The first protocol stack and the second protocol stack may exchange packets to facilitate communications via both the first PHY layer and the second PHY layer. In another embodiment, the first PHY layer is for communication according to the PCIe™ communication protocol and the second PHY layer is for communication according to another, comparatively low power communication protocol.

Abstract: Techniques for transmitted data through a USB port using a PCIe protocol are described herein. In one example, an apparatus includes a host controller, a root port, a multiplexor coupled to the host controller and the root port and a power delivery module. The power delivery module and the multiplexor can transmit and receive a request via a multimode input/output (I/O) interface and the power delivery module can detect a presence of an external device in response to the external device being coupled to the multimode I/O interface. The power delivery module can also send a first request to the external device to discover a vendor identifier of the external device, send a second request to discover at least one alternate mode supported by the external device, and send a third request to enable data transfer via the protocol.

Abstract: Techniques for transmitted data through a USB port using a PCIe protocol are described herein. In one example, a method includes detecting a coupling of an apparatus and a PCIe compatible device via a Type-C connector and sending at least one vendor defined message to the PCIe compatible device. The method can also include receiving an alternate mode indicator corresponding to a data transfer via a PCIe protocol and sending an enter mode command to the PCIe compatible device to enable the data transfer between the apparatus and the PCIe compatible device via the PCIe protocol. Furthermore, the method can include transferring data between the apparatus and the PCIe compatible device via the Type-C connector with the PCIe protocol.

Abstract: An interconnect switch is provided including switching logic executable to facilitate a Peripheral Component Interconnect Express (PCIe)-based interconnect, and further including a control host embedded in the switch to provide one or more enhanced routing capabilities. The control host includes a processor device, memory, and software executable by the processor device to process traffic received at one or more ports of the switch to redirect at least a portion of the traffic to provide the one or more enhanced routing capabilities.

Abstract: Method, apparatus, and systems employing novel dictionary entry replacement schemes for dictionary-based high-bandwidth lossless compression. A pair of dictionaries having entries that are synchronized and encoded to support compression and decompression operations are implemented via logic at a compressor and decompressor. The compressor/decompressor logic operatives in a cooperative manner, including implementing the same dictionary update schemes, resulting in the data in the respective dictionaries being synchronized. The dictionaries are also configured with replaceable entries, and replacement policies are implemented based on matching bytes of data within sets of data being transferred over the link. Various schemes are disclosed for entry replacement, as well as a delayed dictionary update technique. The techniques support line-speed compression and decompression using parallel operations resulting in substantially no latency overhead.

Abstract: A device to process data packets for communication across PHY layers which are of different respective communication protocols. In an embodiment, the device includes a first protocol stack and a second protocol stack which are each for a PCIe™ communication protocol. The first protocol stack and a second protocol stack may interface, respectively, with a first physical (PHY) layer and a second PHY layer of the device. The first protocol stack and the second protocol stack may exchange packets to facilitate communications via both the first PHY layer and the second PHY layer. In another embodiment, the first PHY layer is for communication according to the PCIe™ communication protocol and the second PHY layer is for communication according to another, comparatively low power communication protocol.

Abstract: A device to process data packets for communication across PHY layers which are of different respective communication protocols. In an embodiment, the device includes a first protocol stack and a second protocol stack which are each for a PCIe™ communication protocol. The first protocol stack and a second protocol stack may interface, respectively, with a first physical (PHY) layer and a second PHY layer of the device. The first protocol stack and the second protocol stack may exchange packets to facilitate communications via both the first PHY layer and the second PHY layer. In another embodiment, the first PHY layer is for communication according to the PCIe™ communication protocol and the second PHY layer is for communication according to another, comparatively low power communication protocol.

Abstract: Techniques for transmitted data through a USB port using a PCIe protocol are described herein. In one example, an apparatus includes a host controller, a root port, a multiplexor coupled to the host controller and the root port and a power delivery module. The power delivery module and the multiplexor can transmit and receive a request via a multimode input/output (I/O) interface and the power delivery module can detect a presence of an external device in response to the external device being coupled to the multimode I/O interface. The power delivery module can also send a first request to the external device to discover a vendor identifier of the external device, send a second request to discover at least one alternate mode supported by the external device, and send a third request to enable data transfer via the protocol.

Abstract: Techniques for transmitted data through a USB port using a PCIe protocol are described herein. In one example, a method includes detecting a coupling of an apparatus and a PCIe compatible device via a Type-C connector and sending at least one vendor defined message to the PCIe compatible device. The method can also include receiving an alternate mode indicator corresponding to a data transfer via a PCIe protocol and sending an enter mode command to the PCIe compatible device to enable the data transfer between the apparatus and the PCIe compatible device via the PCIe protocol. Furthermore, the method can include transferring data between the apparatus and the PCIe compatible device via the Type-C connector with the PCIe protocol.

Abstract: Method, apparatus, and systems employing dictionary-based high-bandwidth lossless compression. A pair of dictionaries having entries that are synchronized and encoded to support compression and decompression operations are implemented via logic at a compressor and decompressor. The compressor/decompressor logic operatives in a cooperative manner, including implementing the same dictionary update schemes, resulting in the data in the respective dictionaries being synchronized. The dictionaries are also configured with replaceable entries, and replacement policies are implemented based on matching bytes of data within sets of data being transferred over the link. Various schemes are disclosed for entry replacement, as well as a delayed dictionary update technique. The techniques support line-speed compression and decompression using parallel operations resulting in substantially no latency overhead.

Abstract: Method, apparatus, and systems employing novel delayed dictionary update schemes for dictionary-based high-bandwidth lossless compression. A pair of dictionaries having entries that are synchronized and encoded to support compression and decompression operations are implemented via logic at a compressor and decompressor. The compressor/decompressor logic operatives in a cooperative manner, including implementing the same dictionary update schemes, resulting in the data in the respective dictionaries being synchronized. The dictionaries are also configured with replaceable entries, and replacement policies are implemented based on matching bytes of data within sets of data being transferred over the link. Various schemes are disclosed for entry replacement, as well as a delayed dictionary update technique. The techniques support line-speed compression and decompression using parallel operations resulting in substantially no latency overhead.

Abstract: A device to process data packets for communication across PHY layers which are of different respective communication protocols. In an embodiment, the device includes a first protocol stack and a second protocol stack which are each for a PCIe™ communication protocol. The first protocol stack and a second protocol stack may interface, respectively, with a first physical (PHY) layer and a second PHY layer of the device. The first protocol stack and the second protocol stack may exchange packets to facilitate communications via both the first PHY layer and the second PHY layer. In another embodiment, the first PHY layer is for communication according to the PCIe™ communication protocol and the second PHY layer is for communication according to another, comparatively low power communication protocol.

Abstract: Method, apparatus, and systems employing dictionary-based high-bandwidth lossless compression. A pair of dictionaries having entries that are synchronized and encoded to support compression and decompression operations are implemented via logic at a compressor and decompressor. The compressor/decompressor logic operatives in a cooperative manner, including implementing the same dictionary update schemes, resulting in the data in the respective dictionaries being synchronized. The dictionaries are also configured with replaceable entries, and replacement policies are implemented based on matching bytes of data within sets of data being transferred over the link. Various schemes are disclosed for entry replacement, as well as a delayed dictionary update technique. The techniques support line-speed compression and decompression using parallel operations resulting in substantially no latency overhead.

Abstract: Method, apparatus, and systems employing dictionary-based high-bandwidth lossless compression. A pair of dictionaries having entries that are synchronized and encoded to support compression and decompression operations are implemented via logic at a compressor and decompressor. The compressor/decompressor logic operatives in a cooperative manner, including implementing the same dictionary update schemes, resulting in the data in the respective dictionaries being synchronized. The dictionaries are also configured with replaceable entries, and replacement policies are implemented based on matching bytes of data within sets of data being transferred over the link. Various schemes are disclosed for entry replacement, as well as a delayed dictionary update technique. The techniques support line-speed compression and decompression using parallel operations resulting in substantially no latency overhead.

Abstract: Method, apparatus, and systems employing novel dictionary entry replacement schemes for dictionary-based high-bandwidth lossless compression. A pair of dictionaries having entries that are synchronized and encoded to support compression and decompression operations are implemented via logic at a compressor and decompressor. The compressor/decompressor logic operatives in a cooperative manner, including implementing the same dictionary update schemes, resulting in the data in the respective dictionaries being synchronized. The dictionaries are also configured with replaceable entries, and replacement policies are implemented based on matching bytes of data within sets of data being transferred over the link. Various schemes are disclosed for entry replacement, as well as a delayed dictionary update technique. The techniques support line-speed compression and decompression using parallel operations resulting in substantially no latency overhead.