Abstract: A semiconductor circuit is disclosed, comprising: a processor; a supply-voltage terminal arranged to receive a supply voltage; an out-of-range-voltage-detection circuit, coupled to the supply-voltage terminal and configured to output a voltage-out-of-range indicator in response to detecting that the supply voltage is out-of-range; a PWM signal generator configured to generate a PWM signal; a power-on-reset request terminal arranged to output the PWM signal during a normal operation of the processor; and logic circuitry between the signal generator and the POR request terminal and configured to modify the PWM signal in response receiving the voltage-out-of-range indicator. A microcontroller circuit incorporating such a semiconductor circuit, and a PMIC circuit for use in conjunction, are also disclosed.

Abstract: A method, power converter and controller are disclosed for controlling a power converter having a main converter connected between a first input voltage and a ground and having a main output at an output terminal, an auxiliary converter connected between a second input voltage and the ground and having an auxiliary output, an output capacitor connected between the main output terminal and a ground, and an auxiliary capacitor connected between the auxiliary output and the main output terminal; and a controller; the method comprising: operating the main converter at a first frequency, operating the auxiliary converter at a second frequency; controlling the main converter to control the voltage at the auxiliary output; and controlling the auxiliary converter to control the voltage at the main output.

Abstract: Disclosed are a controller and power converter having a main buck converter connected between a first input voltage and ground and having a main output, a bidirectional auxiliary converter connected between a second terminal and ground and having an auxiliary output connected to the main output, an output capacitor, and an auxiliary capacitor connected between the second terminal and the ground for providing a second terminal voltage at the second terminal; the controller comprising: first control circuit configured to operate the main converter at a first frequency; and second control circuit configured to operate the auxiliary converter at a higher frequency; the first control circuit being further configured to operate the main converter in dependence on the second terminal voltage; and the second control circuit being further configured to operate the auxiliary converter to control the voltage at the main output terminal.

Abstract: Monitoring for an over-voltage condition based on a regulated voltage is disclosed. A first terminal of a voltage regulator receives a first voltage which is based on a regulated voltage input to a controller. A second terminal of the voltage regulator receives a second voltage indicative of the voltage input to the controller. A determination is made whether the first voltage exceeds the first voltage reference for a first time window and the controller is reset based on the determination that the first voltage exceeds the first voltage reference. A determination is also made whether the second voltage exceeds the second voltage reference for the second time window and the voltage regulator is powered down on based on the determination that the second voltage exceeds the second voltage reference.

Abstract: A system-on-a-chip (SoC) is designed to operate within optimal voltage and frequency ranges. If an SoC is provided power outside of the optimal voltage range, the SoC can be placed in a high-stress state, exposing the chip to a security attack. Embodiments of the present systems and method limit the minimum and maximum voltage supplied to an SoC from a power management integrated circuit (PMIC). Embodiments can also track a number of requests to provide power outside of the optimal range and can signal a warning of repeated attempts to take an SoC outside of the SoC's optimal range, which may be indicative of a malicious attack on the system.

Abstract: Various embodiments relate to a distributed power system, including: a primary power management integrated circuit (PMIC) configured to receive a source voltage and connected to a primary communication bus, wherein the primary PMIC produces a secondary voltage on a voltage line, wherein the primary PMIC communicates with a microcontroller unit (MCU) via the primary communication bus; and a plurality of secondary PMICs connected to the primary PMIC via the voltage line, a secondary communication bus, and a fail line, wherein the plurality of secondary PMICs are configured to produce a pulsed signal on the fail line when a secondary PMIC fails, wherein the pulsed signal produced by each of the plurality of secondary PMICs have a unique pulse width that indicates to the primary PMIC the identity of the failed secondary PMIC.

Abstract: Various embodiments relate to a distributed power system, including: a primary power management integrated circuit (PMIC) configured to receive a source voltage and connected to a primary communication bus, wherein the primary PMIC produces a secondary voltage on a voltage line, wherein the primary PMIC communicates with a microcontroller unit (MCU) via the primary communication bus; and a plurality of secondary PMICs connected to the primary PMIC via the voltage line, a secondary communication bus, and a fail line, wherein the plurality of secondary PMICs are configured to produce a pulsed signal on the fail line when a secondary PMIC fails, wherein the pulsed signal produced by each of the plurality of secondary PMICs have a unique pulse width that indicates to the primary PMIC the identity of the failed secondary PMIC.

Abstract: There are disclosed fault detection circuits and methods for an N-to-1 Dickson topology hybrid DC-DC power converter. A short circuit fault detection circuit comprises: first and second measuring circuits configured to measure first and second voltages, Vsw1, Vsw2, at the switching node in the first and second state; first and second calculation circuits configured to calculate first and second absolute error voltage as an absolute difference of the respective first and second voltages in one operating cycle (Vsw1[n?1], Vsw2[n?1]) and in a next subsequent operating cycle (Vsw1[n], Vsw2[n]); and first and second fault circuits configured to provide first and second fault outputs indicative of a fault in response to the respective first or second absolute error voltage exceeding a short-circuit-trip level. Open circuit fault detection circuits and methods are also disclosed.

Abstract: A method and system are provided for supplying power with an LDO linear voltage regulator (110) having an LDO power supply (114, 115) and a load switch (116) by connecting a power supply voltage (102, 104) to a main core (121) and a standby core (122) in a multi-core low power microcontroller (120) during an active mode so that the standby core receives a first supply voltage that tracks the power supply voltage during the active mode, and upon detecting a standby mode for the multi-core low power microcontroller, disconnecting the power supply voltage from the standby core and connecting a low dropout (LDO) linear power supply voltage to the standby core during the standby mode so that the standby core receives the LDO linear power supply voltage as a second supply voltage during the standby mode.

Abstract: A system-on-a-chip (SoC) is designed to operate within optimal voltage and frequency ranges. If an SoC is provided power outside of the optimal voltage range, the SoC can be placed in a high-stress state, exposing the chip to a security attack. Embodiments of the present systems and method limit the minimum and maximum voltage supplied to an SoC from a power management integrated circuit (PMIC). Embodiments can also track a number of requests to provide power outside of the optimal range and can signal a warning of repeated attempts to take an SoC outside of the SoC's optimal range, which may be indicative of a malicious attack on the system.

Abstract: Disclosed are switched-mode DC-DC power converter modules, SMPC controllers, and distributed-control multiphase SMPC systems. The controller comprises: a reference clock; a synchronisation input configured to receive a first synchronisation signal; a synchronisation output configured to transmit a second synchronisation signal; a control unit configured to control the operation of the SMPC module with a phase determined by the reference clock signal or the first synchronisation signal; a delay line configured to generate the second synchronisation signal by adding a delay to the selected one of the first synchronisation signal and the reference clock signal; a fault detection terminal; a memory configured to store a datum corresponding to a number N of SMPCs in the system; and a delay calculation module configured to calculate the delay in dependence on the datum and the signal at the fault-detection terminal. Associated methods are also disclosed.

Abstract: A method and system are provided for supplying power with an LDO linear voltage regulator (110) having an LDO power supply (114, 115) and a load switch (116) by connecting a power supply voltage (102, 104) to a main core (121) and a standby core (122) in a multi-core low power microcontroller (120) during an active mode so that the standby core receives a first supply voltage that tracks the power supply voltage during the active mode, and upon detecting a standby mode for the multi-core low power microcontroller, disconnecting the power supply voltage from the standby core and connecting a low dropout (LDO) linear power supply voltage to the standby core during the standby mode so that the standby core receives the LDO linear power supply voltage as a second supply voltage during the standby mode.

Abstract: There are disclosed fault detection circuits and methods for an N-to-1 Dickson topology hybrid DC-DC power converter. A short circuit fault detection circuit comprises: first and second measuring circuits configured to measure first and second voltages, Vsw1, Vsw2, at the switching node in the first and second state; first and second calculation circuits configured to calculate first and second absolute error voltage as an absolute difference of the respective first and second voltages in one operating cycle (Vsw1[n?1], Vsw2[n?1]) and in a next subsequent operating cycle (Vsw1[n], Vsw2[n]); and first and second fault circuits configured to provide first and second fault outputs indicative of a fault in response to the respective first or second absolute error voltage exceeding a short-circuit-trip level. Open circuit fault detection circuits and methods are also disclosed.

Abstract: Disclosed are switched-mode DC-DC power converter modules, SMPC controllers, and distributed-control multiphase SMPC systems. The controller comprises: a reference clock; a synchronisation input configured to receive a first synchronisation signal; a synchronisation output configured to transmit a second synchronisation signal; a control unit configured to control the operation of the SMPC module with a phase determined by the reference clock signal or the first synchronisation signal; a delay line configured to generate the second synchronisation signal by adding a delay to the selected one of the first synchronisation signal and the reference clock signal; a fault detection terminal; a memory configured to store a datum corresponding to a number N of SMPCs in the system; and a delay calculation module configured to calculate the delay in dependence on the datum and the signal at the fault-detection terminal. Associated methods are also disclosed.

Abstract: A protection system for an integrated circuit is disclosed. A detection system detects an overvoltage condition and provides an overvoltage condition signal to indicate a condition in which overvoltage protection may be desired. In response to the overvoltage condition signal, one or more variable resistance devices in the system, such as power devices of associated driver circuitry, are controlled to limit the voltage across such devices.

Abstract: A protection system for an integrated circuit is disclosed. A detection system detects an overvoltage condition and provides an overvoltage condition signal to indicate a condition in which overvoltage protection may be desired. In response to the overvoltage condition signal, one or more variable resistance devices in the system, such as power devices of associated driver circuitry, are controlled to limit the voltage across such devices.