Abstract: A serial protocol and interface for data transmission from a data transmitter 12 to a data receiver 14 where the propagation delay may be up to several clock cycles long and may be varying slowly. The data receiver provides a clock to the data transmitter. A synchronization signal provided by either the receiver or the transmitter initiates a frame of data transmission at a transfer rate controlled by the clock. The synchronization signal coordinates the transmission of a data header followed by a predetermined number of data bits, known as the frame length. The data receiver uses the header bits to determine the times to sample the subsequent data bits. The length of the frame is limited to provide sufficient likelihood the propagation delay line characteristics have not changed enough to cause a bit error. The system resynchronizes at the beginning of each frame.

Abstract: A serial protocol and interface for data transmission from a data transmitter 12 to a data receiver 14 where the propagation delay may be up to several clock cycles long and may be varying slowly. The data receiver provides a clock to the data transmitter. A synchronization signal provided by either the receiver or the transmitter initiates a frame of data transmission at a transfer rate controlled by the clock. The synchronization signal coordinates the transmission of a data header followed by a predetermined number of data bits, known as the frame length. The data receiver uses the header bits to determine the times to sample the subsequent data bits. The length of the frame is limited to provide sufficient likelihood the propagation delay line characteristics have not changed enough to cause a bit error. The system resynchronizes at the beginning of each frame.

Abstract: A no-missing-code output from a SAR, pipeline, folding, flash analog to digital conversion can be obtained by providing an analog input to an analog to digital converter having a predetermined m bit resolution output and a predetermined missing code capability and generating in a digital filter from the m bit output and the dither of the random noise components of the m bit output n bit output and greater than the predetermined missing code capability of the analog to digital converter.

Abstract: An amplifier circuit whose input stage (1) has a variable gain and a DC voltage level on its load resistor (Rc), which is stabilized with the aid of means comprising a DC current generator (S), which varies contrary to the average output current of this input stage (1) and which for this purpose supplies a complementary current (I.sub.2) on this load resistor (Rc).The stabilizing means furthermore comprise a high gain differential amplifier (A) of which an input (15) is connected to the active terminal (11) of the load resistor (Rc) and whose output signal is used for the current generator control (S) via a low-pass filter (F) such that that complementary current (I.sub.2) is applied as negative feedback to the input (15) of the differential amplifier (A). An automatic gain control device which utilizes this amplifier circuit is also shown.