Patents by Inventor Alain J. Martin
Alain J. Martin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8605516Abstract: A random access memory (RAM) cell provides a control section and a storage section coupled to the storage section. The storage section includes complementary metal-oxide semiconductor (CMOS) transistors and the storage section is read by precharging the control section to a virtual drain voltage.Type: GrantFiled: January 7, 2010Date of Patent: December 10, 2013Assignee: California Institute of TechnologyInventors: Christopher D. Moore, Sean J. Keller, Alain J. Martin
-
Patent number: 7999567Abstract: Single Event Upset (SEU, also referred to as soft error) tolerant arbiters, bare arbiters, and filters are disclosed. An arbiter provides a filter section, and a bare arbiter, coupled to the filter section. The bare arbiter includes a redundant first input and a redundant second input, and a redundant first output and a redundant second output. A pull-down transistor in the bare arbiter conditionally overpowers a corresponding pull-up transistor in the bare arbiter when a contention condition is present in the bare arbiter.Type: GrantFiled: January 7, 2010Date of Patent: August 16, 2011Assignee: California Institute of TechnologyInventors: Wonjin Jang, Christopher D. Moore, Alain J. Martin
-
Patent number: 7934031Abstract: An asynchronous logic family of circuits which communicate on delay-insensitive flow-controlled channels with 4-phase handshakes and 1 of N encoding, compute output data directly from input data using domino logic, and use the state-holding ability of the domino logic to implement pipelining without additional latches.Type: GrantFiled: May 11, 2006Date of Patent: April 26, 2011Assignee: California Institute of TechnologyInventors: Andrew M. Lines, Alain J. Martin, Uri Cummings
-
Patent number: 7898284Abstract: Asynchronous nanoelectronic circuits that operate according to principles of quasi-delay insensitive design are described. Circuit or logic elements comprising n-type devices are fabricated in a first n-plane, p-type devices are fabricated in a p-plane, and connections are formed in a routing plane of a compute tile. A state-holding element comprising a selected one of a C-element, a precharge function-block, and a read-write register is described. The state-holding element can hold a value of an output of a logic element during a time when the output is disconnected from a reference voltage. Isochronic forks having an adversary path designed to make state transitions safe are explained.Type: GrantFiled: November 14, 2007Date of Patent: March 1, 2011Assignee: California Institute of TechnologyInventors: Alain J. Martin, Piyush Prakash
-
Publication number: 20100283502Abstract: Asynchronous nanoelectronic circuits that operate according to principles of quasi-delay insensitive design are described. Circuit or logic elements comprising n-type devices are fabricated in a first n-plane, p-type devices are fabricated in a p-plane, and connections are formed in a routing plane of a compute tile. A state-holding element comprising a selected one of a C-element, a precharge function-block, and a read-write register is described. The state-holding element can hold a value of an output of a logic element during a time when the output is disconnected from a reference voltage. Isochronic forks having an adversary path designed to make state transitions safe are explained.Type: ApplicationFiled: November 14, 2007Publication date: November 11, 2010Applicant: California Institute of Technology.Inventors: Alain J. Martin, Piyush Prakash
-
Publication number: 20100176841Abstract: Single Event Upset (SEU, also referred to as soft error) tolerant arbiters, bare arbiters, and filters are disclosed. An arbiter provides a filter section, and a bare arbiter, coupled to the filter section. The bare arbiter includes a redundant first input and a redundant second input, and a redundant first output and a redundant second output. A pull-down transistor in the bare arbiter conditionally overpowers a corresponding pull-up transistor in the bare arbiter when a contention condition is present in the bare arbiter.Type: ApplicationFiled: January 7, 2010Publication date: July 15, 2010Applicant: California Institute of TechnologyInventors: Wonjin Jang, Christopher D. Moore, Alain J. Martin
-
Publication number: 20100172195Abstract: A random access memory (RAM) cell provides a control section and a storage section coupled to the storage section. The storage section includes complementary metal-oxide semiconductor (CMOS) transistors and the storage section is read by precharging the control section to a virtual drain voltage.Type: ApplicationFiled: January 7, 2010Publication date: July 8, 2010Applicant: California Institute of TechnologyInventors: Christopher D. Moore, Sean J. Keller, Alain J. Martin
-
Patent number: 7721183Abstract: The invention provides circuits that are tolerant to soft errors, such as a single event upset (SEU). The circuits have a chain of permitted state changes. Redundant elements, including redundant literals and assignments, are designed and implemented in the circuit. The design is such that a disruption or change of state on a single element by an SEU will not change the state flow of a circuit or lead to impermissible state changes. In one embodiment, the invention is implemented in quasi-delay-insensitive (QDI) asynchronous circuits.Type: GrantFiled: August 30, 2005Date of Patent: May 18, 2010Assignee: California Institute of TechnologyInventors: Alain J. Martin, Wonjin Jang, Mika Nystroem
-
Patent number: 7404172Abstract: The present invention is a systematic and data-driven-decomposition (DDD) method and apparatus for use in VLSI synthesis. The invention decomposes a high level program circuit description into a collection of small and highly concurrent modules that can be implemented directly into transistor networks. This enables an automatic implementation of a decomposition process currently done by hand. Unlike prior art syntax-based decompositions, the method of the present invention examines data dependencies in the process' computation, and then attempts to eliminate unnecessary synchronization in the system. In one embodiment, the method comprises: a conversion to convert the input program into an intermediate Dynamic Single Assignment (DSA) form, a projection process to decompose the intermediate DSA into smaller concurrent processes, and a clustering process that optimally groups small concurrent processes to make up the final decomposition.Type: GrantFiled: December 19, 2003Date of Patent: July 22, 2008Assignee: California Institute of TechnologyInventors: Catherine G. Wong, Mika Nystroem, Alain J. Martin
-
Patent number: 7301362Abstract: Systems and methods for mitigating the effects of soft errors in asynchronous digital circuits. Circuits are constructed using stages comprising doubled logic elements which are connected to c-elements that compare the output states of the double logic elements. The inputs of logic elements in a stage are inhibited from changing until the outputs of the c-elements of that stage are enabled. The c-elements inhibit the propagation of a soft error by halting the operation of the circuit until the temporary effects of the soft error pass.Type: GrantFiled: March 14, 2006Date of Patent: November 27, 2007Assignee: California Institute of TechnologyInventors: Wonjin Jang, Alain J. Martin, Mika Nystroem, Jonathan A. Dama
-
Patent number: 6949954Abstract: The present invention is a class of circuits named asynchronous pulse logic (APL) circuit and designing methods for such circuits. APL replaces two of the four-phase handshakes in QDI circuits with pulses, thus breaking the timing dependencies that cause performance problems in QDI circuits. Since the pulse length in APL varies so little, it can be assumed constant. This assumption frees designers from needing to consider the effects of the inputs and outputs on the pulse length, which means timing properties can be verified locally. One embodiment of the present invention is a class of circuit design called the single-track-handshake-asynchronous-pulse-logic (STAPL), which serves as a new target for the compilation of CHP (Communication Hardware Process) programs. In one embodiment, a five-stage pulse generator is used to create a 10 transition count cycle circuit. Advantages of STAPL include a simplified solution to the charge-sharing problem and less loading from p-transistors.Type: GrantFiled: October 24, 2003Date of Patent: September 27, 2005Assignee: California Institute of TechnologyInventors: Mika Nyström, Alain J. Martin
-
Publication number: 20040158802Abstract: The present invention is a systematic and data-driven-decomposition (DDD) method and apparatus for use in VLSI synthesis. The invention decomposes a high level program circuit description into a collection of small and highly concurrent modules that can be implemented directly into transistor networks. This enables an automatic implementation of a decomposition process currently done by hand. Unlike prior art syntax-based decompositions, the method of the present invention examines data dependencies in the process' computation, and then attempts to eliminate unnecessary synchronization in the system. In one embodiment, the method comprises: a conversion to convert the input program into an intermediate Dynamic Single Assignment (DSA) form, a projection process to decompose the intermediate DSA into smaller concurrent processes, and a clustering process that optimally groups small concurrent processes to make up the final decomposition.Type: ApplicationFiled: December 19, 2003Publication date: August 12, 2004Inventors: Catherine G. Wong, Mika Nystroem, Alain J. Martin
-
Patent number: 6732336Abstract: The present invention is a class of circuits named asynchronous pulse logic (APL) circuit and designing methods for such circuits. APL replaces two of the four-phase handshakes in QDI circuits with pulses, thus breaking the timing dependencies that cause performance problems in QDI circuits. Since the pulse length in APL varies so little, it can be assumed constant. This assumption frees designers from needing to consider the effects of the inputs and outputs on the pulse length, which means timing properties can be verified locally. One embodiment of the present invention is a class of circuit design called the single-track-handshake-asynchronous-pulse-logic (STAPL), which serves as a new target for the compilation of CHP (Communication Hardware Process) programs. In one embodiment, a five-stage pulse generator is used to create a 10 transition count cycle circuit. Advantages of STAPL include a simplified solution to the charge-sharing problem and less loading from p-transistors.Type: GrantFiled: October 11, 2002Date of Patent: May 4, 2004Assignee: California Institute of TechnologyInventors: Mika Nyström, Alain J. Martin
-
Patent number: 6711717Abstract: The present invention is a programming language method called Pipeline Language 1 (PL1) and its associated compiler system for generating logical circuit designs. The semantics allow the implementation to add more slack than exists in the specification, aiding the design of slack-elastic systems. In PL1, the value probe and peek are the most basic operations: receiving a value is done by first using the peek, and then acknowledging it as a separate action. Another embodiment is a PL1 compiler comprised of a technology-independent front-end module and a technology-dependent back-end module. It parses the input, converts it into BDD expressions, checks determinism conditions, generates BDD expressions for assignments and sends and converts the BDD expressions to unary representation. The back-end compiler module is technology-dependent, meaning that different back-end modules generate different circuit design types (e.g. QDI and STAPL).Type: GrantFiled: October 11, 2002Date of Patent: March 23, 2004Assignee: California Institute of TechnologyInventors: Mika Nyström, Alain J. Martin
-
Publication number: 20040030858Abstract: An asynchronous processor that has reshuffled processes to implement precharge logic.Type: ApplicationFiled: July 18, 2001Publication date: February 12, 2004Inventors: Andrew M. Lines, Alain J. Martin, Uri Cummings
-
Patent number: 6690203Abstract: Unlike prior art synchronizers and asynchronous arbiters that produce glitches in their outputs, the present invention provides a failure-free synchronizer that can sample an arbitrary and unstable inputs while maintaining zero probability of system failure. In particular, the invention addresses the synchronization failure problem and the lack of a metastable state in prior art synchronizers. Prior attempts have shown that the conditions rex and rex (where re is the control input and x is the data input) cannot be arbitrated. To overcome this, embodiments of the present invention introduce explicit signals a0 and a1 to hold the values rex and rex, respectively. One embodiment is a fast synchronizer. It has four main components—an input integrator, an inverting component, a SEL component and an output filter. Another embodiment of the present invention is a safe synchronizer that meets the strictest QDI design requirements. Other embodiments use a standard arbiter and a killable arbiter for arbitration.Type: GrantFiled: December 28, 2001Date of Patent: February 10, 2004Assignee: California Institute of TechnologyInventors: Mika Nyström, Rajit Manohar, Alain J. Martin
-
Publication number: 20030233622Abstract: The present invention is a class of circuits named asynchronous pulse logic (APL) circuit and designing methods for such circuits. APL replaces two of the four-phase handshakes in QDI circuits with pulses, thus breaking the timing dependencies that cause performance problems in QDI circuits. Since the pulse length in APL varies so little, it can be assumed constant. This assumption frees designers from needing to consider the effects of the inputs and outputs on the pulse length, which means timing properties can be verified locally. One embodiment of the present invention is a class of circuit design called the single-track-handshake-asynchronous-pulse-logic (STAPL), which serves as a new target for the compilation of CHP (Communication Hardware Process) programs. In one embodiment, a five-stage pulse generator is used to create a 10 transition count cycle circuit. Advantages of STAPL include a simplified solution to the charge-sharing problem and less loading from p-transistors.Type: ApplicationFiled: October 11, 2002Publication date: December 18, 2003Inventors: Mika Nystrom, Alain J. Martin
-
Patent number: 6658550Abstract: An asynchronous processor having pipelined instruction fetching and execution to implement concurrent execution of instructions by two or more execution units. A writeback unit is connected to execution units and memory units to control information updates and to handle precise exception. A pipelined completion mechanism can be implemented to improve the throughput.Type: GrantFiled: April 30, 2002Date of Patent: December 2, 2003Assignee: California Institute of TechnologyInventors: Alain J. Martin, Andrew Lines, Rajit Manohar, Uri Cummings, Mika Nystroem
-
Publication number: 20030172360Abstract: The present invention is a programming language method called Pipeline Language 1 (PL1) and its associated compiler system for generating logical circuit designs. The semantics allow the implementation to add more slack than exists in the specification, aiding the design of slack-elastic systems. In PL1, the value probe and peek are the most basic operations: receiving a value is done by first using the peek, and then acknowledging it as a separate action. Another embodiment is a PL1 compiler comprised of a technology-independent front-end module and a technology-dependent back-end module. It parses the input, converts it into BDD expressions, checks determinism conditions, generates BDD expressions for assignments and sends and converts the BDD expressions to unary representation. The back-end compiler module is technology-dependent, meaning that different back-end modules generate different circuit design types (e.g. QDI and STAPL).Type: ApplicationFiled: October 11, 2002Publication date: September 11, 2003Inventors: Mika Nystrom, Alain J. Martin
-
Publication number: 20030140214Abstract: An asynchronous circuit having a pipelined completion mechanism to achieve improved throughput.Type: ApplicationFiled: December 31, 2002Publication date: July 24, 2003Applicant: California Institute of TechnologyInventors: Alain J. Martin, Andrew M. Lines, Uri V. Cummings