Abstract: An apparatus and process for updating a sample time in a serial link which converts serial data in parallel data. A delay line stores multiple samples of at least two data bits received over the serial link. The contents of the delay line are matched so that they can be analyzed by a processor to determine an optimum sampling position in the delay line. The processor is programmed to analyze contents of the latch by creating a sample mask from a plurality of delay line samples. The sample mask identifies transition edges of first and second data bits within the delay line. The transition edges are validated with respect to the presence, for first and second initial sampling positions for the respective data bits. New sampling positions are determined from the validated edges, and the initial sampling positions are updated with sampling positions which have been determined from the new sampling positions.