Patents by Inventor Alain Straboni
Alain Straboni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9741881Abstract: A photovoltaic module and its manufacturing method. The module includes a first support wafer made of sintered silicon and a second layer of single-crystal silicon.Type: GrantFiled: December 28, 2015Date of Patent: August 22, 2017Assignee: S'TILEInventors: Alain Straboni, Emmanuel Turlot
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Patent number: 9493358Abstract: A photovoltaic module and its manufacturing method. The module includes a sintered silicon support including several integrated photovoltaic cells.Type: GrantFiled: November 24, 2010Date of Patent: November 15, 2016Assignee: STileInventors: Alain Straboni, Emmanuel Turlot
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Publication number: 20160118507Abstract: A photovoltaic module and its manufacturing method. The module includes a first support wafer made of sintered silicon and a second layer of single-crystal silicon.Type: ApplicationFiled: December 28, 2015Publication date: April 28, 2016Inventors: Alain Straboni, Emmanuel Turlot
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Patent number: 9230806Abstract: The present invention relates to a method for forming a crystallized silicon layer made up of grains having an average size of no less than 20 ?m, including at least the steps that comprise: (1) providing a layer of silicon to be (re)crystallized, the average grain size of which is less than 10 ?m; (2) placing said layer of silicon to be (re)crystallized in contact with a liquid composition at least partially made up of a metal solvent; and (3) exposing the assembly to a thermal treatment suitable for (re)crystallizing said layer of silicon with the expected grain size, characterized in that said thermal treatment includes heating the assembly made up of the layer of silicon in contact with said liquid composition to a temperature that is lower than 1410° C. and at least equal to the eutectic temperature in the solvent-silicon phase diagram.Type: GrantFiled: April 8, 2013Date of Patent: January 5, 2016Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, S'TileInventors: Jean-Paul Garandet, Virginie Brize, Etienne Pihan, Alain Straboni, Florent Dupont
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Publication number: 20150079772Abstract: The present invention relates to a method for forming a crystallised silicon layer made up of grains having an average size of no less than 20 ?m, including at least the steps that comprise: (1) providing a layer of silicon to be (re)crystallised, the average grain size of which is less than 10 ?m; (2) placing said layer of silicon to be (re)crystallised in contact with a liquid composition at least partially made up of a metal solvent; and (3) exposing the assembly to a thermal treatment suitable for (re)crystallising said layer of silicon with the expected grain size, characterised in that said thermal treatment includes heating the assembly made up of the layer of silicon in contact with said liquid composition to a temperature that is lower than 1410° C. and at least equal to the eutectic temperature in the solvent-silicon phase diagram.Type: ApplicationFiled: April 8, 2013Publication date: March 19, 2015Inventors: Jean-Paul Garandet, Virginie Brize, Etienne Pihan, Alain Straboni, Florent Dupont
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Patent number: 8975093Abstract: The instant disclosure relates to a device and method for recrystallising a silicon wafer or a wafer comprising at least one silicon layer. The silicon wafer or the at least one silicon layer of the wafer is totally molten.Type: GrantFiled: July 22, 2010Date of Patent: March 10, 2015Assignee: S'TileInventor: Alain Straboni
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Patent number: 8405183Abstract: An electronic structure includes a first area having silicon grains having a size smaller than 100 micrometers and a second area superposed to the first area and having silicon grains having a size greater than or equal to 100 micrometers. The first and second areas form a support. At least one layer of an epitaxial semiconductor material is disposed on the second area.Type: GrantFiled: April 14, 2010Date of Patent: March 26, 2013Assignee: S'Tile Pole des Eco-IndustriesInventor: Alain Straboni
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Publication number: 20120164760Abstract: The instant disclosure relates to a device and method for recrystallising a silicon wafer or a wafer comprising at least one silicon layer. The silicon wafer or the at least one silicon layer of the wafer is totally molten.Type: ApplicationFiled: July 22, 2010Publication date: June 28, 2012Applicant: S'TileInventor: Alain Straboni
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Patent number: 8192648Abstract: A method of forming a material from a source material including the following steps of grinding the source material to get powders if the source material is not already in the form of powders; sintering the powders with at least one compression step and one thermal processing step; and purifying the material with a gas flow, the gas flow passing through the porosity channels of the material.Type: GrantFiled: August 1, 2008Date of Patent: June 5, 2012Assignee: S'TileInventor: Alain Straboni
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Patent number: 8105923Abstract: The invention relates to a method for forming a semiconductor material obtained by sintering powders and to a semiconductor material. The method comprises a compression and heat treatment stage such that one part of the powder is melted or becomes viscous. The material can be used in the photovoltaic field.Type: GrantFiled: April 9, 2004Date of Patent: January 31, 2012Assignees: Centre National de la Recherche Scientifique, Universite de PoitiersInventor: Alain Straboni
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Publication number: 20110186111Abstract: A photovoltaic module and its manufacturing method. The module includes a sintered silicon support including several integrated photovoltaic cells.Type: ApplicationFiled: November 24, 2010Publication date: August 4, 2011Applicant: S'TileInventors: Alain Straboni, Emmanuel Turlot
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Publication number: 20100258172Abstract: An electronic structure includes a first area having silicon grains having a size smaller than 100 micrometers and a second area superposed to the first area and having silicon grains having a size greater than or equal to 100 micrometers. The first and second areas form a support. At least one layer of an epitaxial semiconductor material is disposed on the second area.Type: ApplicationFiled: April 14, 2010Publication date: October 14, 2010Applicant: S'TILEInventor: Alain Straboni
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Patent number: 7563404Abstract: The invention relates to a method for the production of semiconductor granules comprising a step in which semiconductor powders are sintered and/or melted. The powders are nanometric and/or micrometric sized.Type: GrantFiled: April 9, 2004Date of Patent: July 21, 2009Assignees: Centre National de la Recherche Scientifique, Universite de PoitiersInventor: Alain Straboni
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Publication number: 20090039319Abstract: A method of forming a material from a source material including the following steps of grinding the source material to get powders if the source material is not already in the form of powders; sintering the powders with at least one compression step and one thermal processing step; and purifying the material with a gas flow, the gas flow passing through the porosity channels of the material.Type: ApplicationFiled: August 1, 2008Publication date: February 12, 2009Applicant: S'TILEInventor: Alain Straboni
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Publication number: 20090028740Abstract: A method of manufacturing a semiconductor material in the form of bricks or granules, includes a step of sintering powders of at least one material selected from the group consisting of silicon, germanium, gallium arsenide, and the alloys thereof so as to form said granules. The sintering step includes the steps of compacting and thermal processing the powders, and a step of purifying the semiconductor material using a flow of a gas. The gas flow passes through the porosity channels of the material.Type: ApplicationFiled: August 1, 2008Publication date: January 29, 2009Applicant: S'TILEInventor: Alain Straboni
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Publication number: 20070178675Abstract: The invention relates to a method for forming a semiconductor material obtained by sintering powders and to a semiconductor material. The method comprises a compression and heat treatment stage such that one part of the powder is melted or becomes viscous. The material can be used in the photovoltaic field.Type: ApplicationFiled: April 9, 2004Publication date: August 2, 2007Inventor: Alain Straboni
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Publication number: 20070023979Abstract: The invention relates to a method for the production of semiconductor granules comprising a step in which semiconductor powders are sintered and/or melted.Type: ApplicationFiled: April 9, 2004Publication date: February 1, 2007Inventor: Alain Straboni
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Patent number: 5300455Abstract: An integrated circuit such as a MOS transistor, having an electrically conductive diffusion barrier at the metal/silicon interface and a method of manufacture therefor is disclosed. The metal/silicon interface is formed by selective metal deposition onto silicon. According to the method, the interface is subjected to a nitrogen-based plasma during a period of at least five minutes. The interface is brought to a temperature greater than 500.degree. C. during this period, in order to create a diffusion barrier comprising a silicon nitride layer. The interface is then subjected to an annealing treatment under a neutral atmosphere so as to remove the nitrogen previously introduced into the metal. The diffusion barrier forms a linking and protecting interface between each source drain or gate zone of the MOS transistor and the corresponding layer of metal covering the latter.Type: GrantFiled: December 13, 1991Date of Patent: April 5, 1994Assignee: France TelecomInventors: Bernard Vuillermoz, Mouloud Bakli, Alain Straboni
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Patent number: 5229318Abstract: The invention relates to a process for buried localized oxidation of a silicon substrate. The process consists in performing a) a sealing on the surface of the substrate (S), by a first nitriding, by growing a later of silicon nitride forming at least one surface layer, then in performing b) the etching (G1) of a trench (T) intended to receive the buried localized oxidation. A second nitriding is performed c) on the free area of the trench (T) in order to obtain a sealing sc of the walls of the trench (T). An etching (G2) is performed at d) on the bottom wall of the trench (T) by at least partial etching of the silicon nitride layer obtained by second nitriding in order to uncover the substrate material (S). A localized oxidation e) is performed to produce the buried oxidation (OE) of the substrate in the trench. Application to the production of integrated circuits.Type: GrantFiled: February 6, 1992Date of Patent: July 20, 1993Assignee: France TelecomInventors: Alain Straboni, Kathy Barla, Bernard Vuillermoz