Patents by Inventor Alan A. Hale
Alan A. Hale has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240176898Abstract: Embodiments provide a method executed by a secure remote direct memory (RDMA) system. The method includes detecting, by the secure RDMA system, a connection request to create an encrypted connection between a first computing device and a second computing device. An encryption key is shared between the first computing device and the second computing device. In response to sharing the encryption key, accessing a plurality of images of a plurality of memories of the second computing device. The plurality of images of the plurality of memories includes memory addresses. The method includes receiving an access request specifying a range of memory addresses from the first computing device based on accessing the plurality of images of the plurality of memories. The method includes creating an encrypted tunnel between the first computing device and the second computing device to share memory information based on the range of memory addresses of the plurality of memories, in response to the access request.Type: ApplicationFiled: November 29, 2023Publication date: May 30, 2024Inventors: Robert W. Hale, Kyle Alan Borowski, Mathew Lee VanDerPol
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Publication number: 20240179122Abstract: Embodiments provide a system for managing traffic packets of application components. The system includes a security controller. The security controller may be coupled to a plurality of application components. The security controller includes one or more memories and a plurality of processors. The one or more memories are operable to store a set of application components features of each application component of the plurality of application components. The processors may be coupled with the memories and a processor may be configured to perform one or more steps. The processor receives traffic packets from a set of the plurality of application components coupled to the security controller. The processor receives traffic packets from a set of the plurality of application components coupled to the security controller.Type: ApplicationFiled: November 29, 2023Publication date: May 30, 2024Inventors: Robert W. Hale, Kyle Alan Borowski
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Patent number: 11920347Abstract: A joist assembly system that is structured for dynamic retrieval of components, dynamic and precise positioning and location of retrieved components, assembly of the components to form a joist, and delivery of the assembled joist. The joist assembly system has a plurality of material handling systems, a plurality of welding systems, and a rigging table system. The material handling systems are structured to load and position the components such as chords and webs onto the rigging table. The rigging table in turn supports the chords or webs. Subsequently, the plurality of welding systems weld the webs to the chords to form the joist.Type: GrantFiled: May 13, 2022Date of Patent: March 5, 2024Assignee: NUCOR CORPORATIONInventors: Jason Alan Freidenberger, Joseph Patrick Cagle, Christopher Ray Couch, Richard Thomas Erickson, Travis Marshall Fuhrman, John Lyman Hale, Matthew Glenn Hire, Christopher William Martin, James E. Ogburn, III, Jonathan Pressley Poston, Peter Michael Puglisi, Phillip Murray Sylvester, Jr., Adam Taylor Watkins
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Patent number: 11761229Abstract: A tent cover system for providing improved ventilation and cooling is disclosed. The tent cover system includes a frame having a hub and a plurality of roof poles extending therefrom; a cover having a reflective topside and a blackout underside; a plurality of vertical poles configured to hoist the cover above a tent, thereby creating an airspace therebetween; and a plurality of guy lines configured to removably secure the cover to a ground surface.Type: GrantFiled: November 18, 2021Date of Patent: September 19, 2023Inventor: Alan Hale
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Patent number: 10120025Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.Type: GrantFiled: October 27, 2017Date of Patent: November 6, 2018Assignee: Texas Instruments IncorporatedInventors: Lee D. Whetsel, Alan Hales
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Publication number: 20180052202Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.Type: ApplicationFiled: October 27, 2017Publication date: February 22, 2018Inventors: Lee D. Whetsel, Alan Hales
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Patent number: 9829538Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.Type: GrantFiled: December 22, 2016Date of Patent: November 28, 2017Assignee: Texas Instruments IncorporatedInventors: Lee D. Whetsel, Alan Hales
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Patent number: 9702935Abstract: Apparatus and method for testing an integrated circuit. An integrated circuit includes circuitry to be tested, scan chain logic, and a test adapter. The scan chain logic is configured to transfer test data to and test results from the circuitry. The test adapter is configured to extract the test data from a packet received from an automated test control system and to transfer the test data to the scan chain logic. The test adapter is also configured to receive the test results from the scan chain logic, and to packetize the test result for transmission to the automated test control system.Type: GrantFiled: August 29, 2014Date of Patent: July 11, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Lewis Nardini, Sumant Kale, Alan Hales
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Publication number: 20170102430Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.Type: ApplicationFiled: December 22, 2016Publication date: April 13, 2017Inventors: Lee D. Whetsel, Alan Hales
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Patent number: 9562946Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.Type: GrantFiled: March 23, 2016Date of Patent: February 7, 2017Assignee: Texas Instruments IncorporatedInventors: Lee D. Whetsel, Alan Hales
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Publication number: 20160202319Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.Type: ApplicationFiled: March 23, 2016Publication date: July 14, 2016Inventors: Lee D. Whetsel, Alan Hales
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Patent number: 9322879Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.Type: GrantFiled: July 6, 2015Date of Patent: April 26, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Lee D. Whetsel, Alan Hales
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Publication number: 20150309117Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.Type: ApplicationFiled: July 6, 2015Publication date: October 29, 2015Inventors: Lee D. Whetsel, Alan Hales
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Integrated circuit with plural comparators receiving expected data and mask data from different pads
Patent number: 9103885Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.Type: GrantFiled: September 23, 2014Date of Patent: August 11, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Lee D. Whetsel, Alan Hales -
Publication number: 20150067426Abstract: Apparatus and method for testing an integrated circuit. An integrated circuit includes circuitry to be tested, scan chain logic, and a test adapter. The scan chain logic is configured to transfer test data to and test results from the circuitry. The test adapter is configured to extract the test data from a packet received from an automated test control system and to transfer the test data to the scan chain logic. The test adapter is also configured to receive the test results from the scan chain logic, and to packetize the test result for transmission to the automated test control system.Type: ApplicationFiled: August 29, 2014Publication date: March 5, 2015Inventors: Lewis Nardini, Sumant Kale, Alan Hales
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Publication number: 20150012790Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.Type: ApplicationFiled: September 23, 2014Publication date: January 8, 2015Applicant: Texas Instruments IncorporatedInventors: Lee D. Whetsel, Alan Hales
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Publication number: 20140350111Abstract: Methods for treatment of and prophylaxis against hemorrhoids are disclosed, including methods of treatment of and prophylaxis against hemorrhoids comprising administering naproxen to an individual.Type: ApplicationFiled: September 7, 2012Publication date: November 27, 2014Inventor: Guy Alan Hale
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Patent number: 8872178Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.Type: GrantFiled: February 24, 2014Date of Patent: October 28, 2014Assignee: Texas Instruments IncorporatedInventors: Lee D. Whetsel, Alan Hales
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Publication number: 20140167792Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.Type: ApplicationFiled: February 24, 2014Publication date: June 19, 2014Applicant: Texas Instruments IncorporatedInventors: Lee D. Whetsel, Alan Hales
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Patent number: D939657Type: GrantFiled: October 11, 2019Date of Patent: December 28, 2021Inventor: Alan Hale