Abstract: Methods and systems for optimizing the selection of memory blocks for garbage collection to maximize the amount of memory freed by garbage collection operations are disclosed. Some of these systems and methods provide for the efficient selection of optimal or near-optimal garbage collection candidate blocks, with the most optimal selection defined as block(s) with the most invalid pages. In some cases, a controller classifies memory blocks into various invalid block pools by the amount of invalid pages each block contains. When garbage collection is performed, the controller selects a block from a non-empty pool of blocks with the highest minimum amount of invalid pages. The pools facilitate the optimal or near-optimal selection of garbage collection candidate blocks in an efficient manner and the data structure of the pools can be implemented with bitmasks, which take minimal space in memory.

Abstract: A non-volatile semiconductor memory is disclosed comprising a first memory device having a memory array including a plurality of memory segments, and a data register for storing write data prior to being written to one of the memory segments. A memory controller comprises a microprocessor for executing access commands received from a host. Interface circuitry generates control signals that enable the microprocessor to communicate with the first memory device. Power fail circuitry transmits a flush command to the first memory device through the interface circuitry in response to a power fail signal, wherein the first memory device responds to the flush command by transferring the write data stored in the data register to the memory segment.

Abstract: A non-volatile semiconductor memory is disclosed comprising a memory device including a plurality of memory segments. A program command is issued to the memory device to program a memory segment, and a program time required to execute the program command is saved. An erase command is issued to the memory device to erase the memory segment, and an erase time required to execute the erase command is saved. A wear leveling algorithm is executed for the memory segment in response to the program time and the erase time.

Abstract: A non-volatile semiconductor memory is disclosed comprising a first memory device including a plurality of memory segments, and control circuitry operable to determine whether a memory segment in the first memory device needs refreshing, and when the memory segment needs refreshing, read data from the memory segment into a data register without rewriting the data.

Abstract: A non-volatile semiconductor memory is disclosed comprising a plurality of paired pages, wherein each pair comprises a first page and a second page. A write command is received from a host comprising write data and a write address. The write address is mapped to a physical address of a selected one of the paired memory pages. The write data is compressed to generate compressed data, and when the compressed data fits in one of the pages of the selected pair, the compressed data is stored in the first page and in the second page of the selected pair in an S-mode.

Abstract: Embodiments of the invention are directed to optimizing the selection of memory blocks for garbage collection to maximize the amount of memory freed by garbage collection operations. The systems and methods disclosed herein provide for the efficient selection of optimal or near-optimal garbage collection candidate blocks, with the most optimal selection defined as block(s) with the most invalid pages. In one embodiment, a controller classifies memory blocks into various invalid block pools by the amount of invalid pages each block contains. When garbage collection is performed, the controller selects a block from a non-empty pool of blocks with the highest minimum amount of invalid pages. The pools facilitate the optimal or near-optimal selection of garbage collection candidate blocks in an efficient manner and the data structure of the pools can be implemented with bitmasks, which take minimal space in memory.

Abstract: A non-volatile semiconductor memory is disclosed comprising a first memory device having a memory array including a plurality of memory segments, and a data register for storing write data prior to being written to one of the memory segments. A memory controller comprises a microprocessor for executing access commands received from a host. Interface circuitry generates control signals that enable the microprocessor to communicate with the first memory device. Power fail circuitry transmits a flush command to the first memory device through the interface circuitry in response to a power fail signal, wherein the first memory device responds to the flush command by transferring the write data stored in the data register to the memory segment.