Abstract: Embodiments of the present disclosure provide a temperature sensor that may be integrated into a memory device along with a 1T1C reference voltage generator to enable the 1T1C reference voltage generator to provide a temperature dependent 1T1C reference voltage to a memory core (e.g., F-RAM memory core) of the memory device. The temperature sensor may detect a temperature of the memory core, and output this information (e.g., as a trim) for use by the 1T1C reference voltage generator in providing a temperature dependent 1T1C reference voltage. In this way, both the P-term and U-term margins of the memory core may be maintained even as a temperature of the memory core increases.

Abstract: A method of operating a memory device that includes the steps of receiving a read command and a target address in a non-volatile memory (NVM) array, in which the NVM array is divided into a plurality of blocks based on row and column addresses, performing a read operation on NVM cells in the target address and coupling an output of each NVM cell read to a sensing circuit, generating a local reference voltage based on a base reference voltage and an adjustment reference voltage corresponding to the target address of the NVM cells being read and a block that the NVM cells belong thereto, and offsetting the base reference voltage with the adjustment reference voltage, and coupling the local reference voltage to the sensing circuit. Other embodiments are also described.

Abstract: Embodiments of the present disclosure provide a temperature sensor that may be integrated into a memory device along with a 1T1C reference voltage generator to enable the 1T1C reference voltage generator to provide a temperature dependent 1T1C reference voltage to a memory core (e.g., F-RAM memory core) of the memory device. The temperature sensor may detect a temperature of the memory core, and output this information (e.g., as a trim) for use by the 1T1C reference voltage generator in providing a temperature dependent 1T1C reference voltage. In this way, both the P-term and U-term margins of the memory core may be maintained even as a temperature of the memory core increases.

Abstract: Semiconductor memory devices and methods of operating the same are provided. The method of operation may include the steps of selecting a ferroelectric memory cell for a read operation, coupling a first pulse signal to interrogate the selected ferroelectric memory cell, the selected ferroelectric memory cell outputting a memory signal to a bit-line in response to the first pulse signal, coupling the memory signal to a first input of a sense amplifier via the bit-line, electrically isolating the sense amplifier from the selected ferroelectric memory cell, and enabling the sense amplifier for sensing after the sense amplifier is electrically isolated from the selected ferroelectric memory cell. Other embodiments are also disclosed.

Abstract: Semiconductor memory devices and methods of operating the same are provided. The method of operation may include the steps of selecting a ferroelectric memory cell for a read operation, coupling a first pulse signal to interrogate the selected ferroelectric memory cell, the selected ferroelectric memory cell outputting a memory signal to a bit-line in response to the first pulse signal, coupling the memory signal to a first input of a sense amplifier via the bit-line, electrically isolating the sense amplifier from the selected ferroelectric memory cell, and enabling the sense amplifier for sensing after the sense amplifier is electrically isolated from the selected ferroelectric memory cell. Other embodiments are also disclosed.

Abstract: Semiconductor memory devices and methods of operating the same are provided. The method of operation may include the steps of selecting a ferroelectric memory cell for a read operation, coupling a first pulse signal to interrogate the selected ferroelectric memory cell, the selected ferroelectric memory cell outputting a memory signal to a bit-line in response to the first pulse signal, coupling the memory signal to a first input of a sense amplifier via the bit-line, electrically isolating the sense amplifier from the selected ferroelectric memory cell, and enabling the sense amplifier for sensing after the sense amplifier is electrically isolated from the selected ferroelectric memory cell. Other embodiments are also disclosed.

Abstract: Semiconductor memory devices and methods of operating the same are provided. The method of operation may include the steps of selecting a ferroelectric memory cell for a read operation, coupling a first pulse signal to interrogate the selected ferroelectric memory cell, the selected ferroelectric memory cell outputting a memory signal to a bit-line in response to the first pulse signal, coupling the memory signal to a first input of a sense amplifier via the bit-line, electrically isolating the sense amplifier from the selected ferroelectric memory cell, and enabling the sense amplifier for sensing after the sense amplifier is electrically isolated from the selected ferroelectric memory cell. Other embodiments are also disclosed.

Abstract: An apparatus that includes a reference generating circuit configured to generate a reference signal for a non-volatile memory (NVM) device, the reference generating circuit including a first circuit comprising at least one metal-oxide-semiconductor capacitor, the first circuit generating a first signal component of the reference signal, and a second circuit comprising at least one ferroelectric capacitor, the second circuit generating a second signal component of the reference signal, in which the second signal component is temperature dependent.

Abstract: A memory device and array which includes a static random access memory (SRAM) circuit coupled to a non-volatile circuit, such as a ferroelectric-RAM (F-RAM) circuit, in which the F-RAM circuit stores a bit of data from the SRAM circuit during power-out periods, the F-RAM circuit is further coupled to bit-line(s) to output the bit of data stored in the F-RAM circuit when operation power is restored.

Abstract: In some implementations, a sensing apparatus for an appliance connector, set forth by way of example and not limitation, includes at least one substrate including one or more openings operative to receive a corresponding number of prongs of the appliance connector. At least one sensor is coupled to the substrate and is operative to sense at least one characteristic of an environment. A transmitter is coupled to the substrate and is operative to transmit one or more signals derived from the at least one sensed characteristic, where the transmitted signals are capable of being received by a receiving device. A power circuit is coupled to the substrate and is operative to provide power to the at least one sensor and to the transmitter, where the power circuit can receive electric current from at least one of the prongs of the appliance connector to drive the transmitter and the sensor.

Abstract: In some implementations, a gasket, set forth by way of example and not limitation, includes a housing having a plurality of openings operative to receive a plurality of prongs of a power connector for an appliance. At least one sensor is operative to sense at least one characteristic of an environment. A transmitter is operative to transmit one or more signals derived from the at least one sensed characteristic, where the transmitted signals are capable of being received by a receiving device. A power circuit is operative to provide power from the electric current to the at least one sensor and the transmitter.

Abstract: In some implementations, a sensing apparatus for an appliance connector, set forth by way of example and not limitation, includes at least one substrate including one or more openings operative to receive a corresponding number of prongs of the appliance connector. At least one sensor is coupled to the substrate and is operative to sense at least one characteristic of an environment. A transmitter is coupled to the substrate and is operative to transmit one or more signals derived from the at least one sensed characteristic, where the transmitted signals are capable of being received by a receiving device. A power circuit is coupled to the substrate and is operative to provide power to the at least one sensor and to the transmitter, where the power circuit can receive electric current from at least one of the prongs of the appliance connector to drive the transmitter and the sensor.

Abstract: In an embodiment, set forth by way of example and not limitation, a power line surge protector circuit includes a first input node, a second input node, a first output node and a second output node; a semiconductor shunt having an avalanche breakdown potential, the shunt being coupled between the first input node and the second input node, whereby a voltage potential between the first input node and the second input node which is in excess of the avalanche breakdown potential shunts current between the first input node and the second input node; and a resettable circuit breaker coupled between the first input node and the shunt.

Abstract: A voltage signal rectifier produces a rectified voltage signal from an input offset voltage signal. The voltage signal rectifier includes input offset, output, and reference nodes, two actively controlled current regulation elements (ACCREs), and two controllers. The input offset node is coupled to the input offset voltage signal. The rectified voltage signal is generated onto the output node. The reference node is coupled to a reference voltage for the input offset and rectified voltage signals. The ACCREs are coupled to the input offset node and one of the ACCREs is coupled to the output node. Each controller is configured to control the one of the ACCREs so that the ACCRE coupled to the output node allows current flow through it when the input offset voltage signal is higher than the rectified voltage signal and the other ACCRE is configured to allows current flow through it when the input offset voltage signal is lower than the rectified voltage signal.

Abstract: A voltage signal rectifier produces a rectified voltage signal from an input offset voltage signal. The voltage signal rectifier includes input offset, output, and reference nodes, two actively controlled current regulation elements (ACCREs), and two controllers. The input offset node is coupled to the input offset voltage signal. The rectified voltage signal is generated onto the output node. The reference node is coupled to a reference voltage for the input offset and rectified voltage signals. The ACCREs are coupled to the input offset node and one of the ACCREs is coupled to the output node. Each controller is configured to control the one of the ACCREs so that the ACCRE coupled to the output node allows current flow through it when the input offset voltage signal is higher than the rectified voltage signal and the other ACCRE is configured to allows current flow through it when the input offset voltage signal is lower than the rectified voltage signal.

Abstract: A power supply for an integrated circuit has first and second energy storage elements and a regulator. The first energy storage element stores energy for application to the integrated circuit. The second energy storage element stores energy at a higher voltage than the energy stored by the first energy storage element. The regulator interconnects the energy storage elements and controls the flow of energy from the second energy storage element to the first energy storage element to regulate the voltage level of the energy stored in the first energy storage element.

Abstract: A power supply creates a voltage difference between high and low power supply rails. The power supply has a voltage signal source, a capacitive coupling element, energy storage element 12, first and second rectifying diodes, a regulator, and bypass means for selectively decreasing the impedance between the voltage signal source and the low power supply rail or increasing the load presented to the voltage signal source. The capacitive coupling element is connected to the voltage signal source. Energy storage element 12 stores energy between the high and low power supply rails. The first rectifying diode is positioned between the capacitive coupling element and energy storage element 12. It is coupled to the voltage signal source through the capacitive coupling element and arranged to favor current flow toward energy storage element 12 from the capacitive coupling element. The second rectifying diode is positioned between the capacitive coupling element and the low power supply rail.

Abstract: A system for conveying a radio frequency (RF) signal from a base station to a detached integrated circuit (IC) has an intermediate resonant circuit and an IC. The intermediate resonant circuit is configured to resonate in response to the RF signal from the base station, reproducing the RF signal. The IC has an integral resonant circuit configured to resonate in response to the reproduced RF signal. The IC and the intermediate resonant circuit are affixed proximate each other. Both are separate from the base station and each other. Either or both of the intermediate resonant circuit and the integral resonant circuit may contact a high magnetic permeability layer. The intermediate resonant circuit may be formed of conductive ink.

Abstract: A rectifier generates a rectified output and a dc power output. The rectifier has an antenna element, a tuning capacitor, a coupling capacitor, first and second rectifying diodes, and a storage capacitor. The antenna element and the tuning capacitor are coupled in parallel and grounded at one terminal. The first rectifying diode is grounded at its anode terminal and the storage capacitor is grounded at one terminal. The coupling capacitor is coupled between the ungrounded terminal of the antenna element and the cathode terminal of the first rectifying diode. The anode terminal of the second rectifying diode is coupled to the cathode terminal of the first rectifying diode. The cathode terminal of the second rectifying diode is coupled to the ungrounded terminal of the storage capacitor. The rectified output is generated between the rectifying diodes. The dc power output is generated between the second rectifying diode and the storage capacitor.

Abstract: An electrical circuit is formed by forming and patterning a conductive layer on a substrate, forming and patterning a conductive layer on another substrate, depositing a dielectric layer on at least a portion of one of conductive layers, mounting an integrated circuit (IC) between the substrates, coupling the IC to the conductive layers, and affixing the substrates together with the conductive layers between the substrates. These are either separate substrates or a unitary substrate. The IC is mounted either to a substrate, a conductive layer, or a dielectric layer. The IC is coupled to the conductive layers either directly or through openings formed in the dielectric layer. An interior conductive layer may be used to couple the IC to the conductive layers.