Abstract: Methods and structure described herein provide for reducing the overall delay of an RS encoder/decoder without changing the essential functionality of the RS encoder/decoder. In one embodiment, a cascade module reduces the combinatorial logical delay by reducing the total number of logical devices. In doing so, the cascade module couples encoder/decoder slices into blocks. A first block of the encoder/decoder slices is selectively operable in parallel with a second block of encoder/decoder slices. The number of encoder/decoder blocks is less than the overall number of encoder/decoder slices. The cascade module may also include a switch that selects encoder/decoder slices as needed, thereby providing for the implementation of the RS encoder/decoder with fewer logical devices.

Abstract: Methods and associated structures for improved erasure correction and detection in digital communication channels utilizing modified Reed-Solomon decoding of encoded digital data. Methods and associated apparatus in accordance with features and aspects hereof perform Galois Field element generation in descending order for Reed-Solomon erasure detection and correction. Real time computation of Galois Field elements in descending order as required for erasure detection and correction features and aspects hereof eliminates the need for costly, complex, large, high speed lookup tables as previously practiced in the art for storing Galois Field element values pre-computed in the same ascending order of reception of the encoded code words. Features and aspects hereof may thus be applied in digital read channel applications including, for example, digital telecommunications receive/read channels and digital data storage read channels.

Abstract: Methods and structure described herein provide for reducing the overall delay of an RS encoder/decoder without changing the essential functionality of the RS encoder/decoder. In one embodiment, a cascade module reduces the combinatorial logical delay by reducing the total number of logical devices. In doing so, the cascade module couples encoder/decoder slices into blocks. A first block of the encoder/decoder slices is selectively operable in parallel with a second block of encoder/decoder slices. The number of encoder/decoder blocks is less than the overall number of encoder/decoder slices. The cascade module may also include a switch that selects encoder/decoder slices as needed, thereby providing for the implementation of the RS encoder/decoder with fewer logical devices.

Abstract: A method of feed-forward DC restoration in a perpendicular magnetic read channel is disclosed. The method generally includes the steps of (A) generating a feed-forward signal by performing a first detection on an input signal, wherein a DC component of the input signal was previously filtered out in the perpendicular magnetic read channel, (B) generating a restored signal by summing the input signal and the feed-forward signal, the summing restoring the DC component previously filtered out and (C) generating an output signal by performing a second detection on the restored signal, wherein the first detection is independent of the second detection.

Abstract: A method of feed-forward DC restoration in a perpendicular magnetic read channel is disclosed. The method generally includes the steps of (A) generating a feed-forward signal by performing a first detection on an input signal, wherein a DC component of the input signal was previously filtered out in the perpendicular magnetic read channel, (B) generating a restored signal by summing the input signal and the feed-forward signal, the summing restoring the DC component previously filtered out and (C) generating an output signal by performing a second detection on the restored signal, wherein the first detection is independent of the second detection.

Abstract: Methods and associated structures for improved erasure correction and detection in digital communication channels utilizing modified Reed-Solomon decoding of encoded digital data. Methods and associated apparatus in accordance with features and aspects hereof perform Galois Field element generation in descending order for Reed-Solomon erasure detection and correction. Real time computation of Galois Field elements in descending order as required for erasure detection and correction features and aspects hereof eliminates the need for costly, complex, large, high speed lookup tables as previously practiced in the art for storing Galois Field element values pre-computed in the same ascending order of reception of the encoded code words. Features and aspects hereof may thus be applied in digital read channel applications including, for example, digital telecommunications receive/read channels and digital data storage read channels.

Abstract: The present invention is a method and system for reducing miscorrections of data in a post-processor. In an embodiment of the invention, the system and method may compare a result of an exact match function and a metric for each row of a reconstructed data block to determine if a correction should be made. An algorithm for performing an exact match function may include a column parity check syndrome, a matched filter error syndrome, and an error mask of the present invention. If a result of an exact match function is an exact match, a priority of correction may be given to the row in which the exact match was produced.

Abstract: An improved error correction code process takes advantage of information available from a post processor. This information is a list of highly probable error event patterns and locations found by employing a list Viterbi or a set of matched filters on Viterbi data. This list of possible errors can be used by the error correction code decoder in an iterative process whenever the correction power of the error correction code decoder is exceeded. If the error correction code decoder cannot correct the data on its first unassisted try, an iterative process is employed which, in essence, modifies the data with potential errors identified from the list created by the post processor and tries the correction process over again. An algorithm may be employed to try each error singly or in combination with other errors. This iterative process continues until a correctable indication is given by the error correction code decoder algorithm.

Abstract: A method for generating constraint codes in a stream of data having a plurality of multi-bit source words, comprising the steps of (A) checking a sequence portion of the multi-bit source words for one or more constraint violations and (B) if no constraint violations are detected, modifying a predetermined portion of each of the multi-bit source words to generate a plurality of corresponding multi-bit code words configured to prevent the constraint violations of the sequence portions across an adjacent two of the multi-bit code words.

Abstract: The present invention is a method and system for reducing miscorrections of data in a post-processor. In an embodiment of the invention, the system and method may compare a result of an exact match function and a metric for each row of a reconstructed data block to determine if a correction should be made. An algorithm for performing an exact match function may include a column parity check syndrome, a matched filter error syndrome, and an error mask of the present invention. If a result of an exact match function is an exact match, a priority of correction may be given to the row in which the exact match was produced.

Abstract: A system determines the root of a polynomial by employing a parallel structure that implements a Chien Search and minimizes the amount of storage required. The location of an error in a codeword can be derived from the root of an error locator polynomial. The performance of the Chien Search is enhanced by the parallel structure, and the location of the error can be easily determined using a simple calculation that preferably includes the cycle count, the parallelism, and the index of the multiplier/summer rank that indicates a root. Multiple ranks of multipliers receive data stored in a single array of data storage units. Multiplier values of each multiplier are based on the elements of a Galois Field. A method configures data storage units, multipliers, summers, and comparators, and performs a Chien Search. The location of an error in a codeword is determined using a simple calculation based on a determined root of an error locator polynomial.

Abstract: Apparatus, and an associated method, for performing error-correction operations to correct errors in a block of block-encoded data. Two ALUs are operable in parallel to perform finite-field mathematical operations and to calculate addresses used pursuant to the error-correction calculations. Instructions pursuant to which the ALUs are operable are stored in a memory device. The instructions are retrieved during operation of error-correcting calculations. The manner by which the error-correcting apparatus operates is alterable by appropriate alteration of the instructions stored at the memory device.

Abstract: A memory array comprised of floating gate, direct write nonvolatile memory cells having cell interiors which are interconnected by successive adjacent rows to share column lines between adjacent columns of cell and thereby reduce the column line pitch.

Abstract: A memory array architecture configured in one form with multiple subarrays addressable by row lines, bank select lines and column select lines, arranged so that no two data word bit positions have a common row line also share common bank select lines. The addition of isolation between the row lines and the row bus combined with the shifting or jogging of the bank select lines in adjacent subarrays ensures that a short circuit or open circuit in a row line no longer effects multiple bits in a common word. The ability to control the effects of manufacturing defects so that they commonly effect no more than a single bit position within a word makes feasible the use of error correction coding techniques within for example integrated circuit ROM type memories.

Abstract: An electronic circuit configured to pass relatively high voltage signals therethrough when enabled, and block both positive and negative signals when appropriately disabled. The features of the circuit are particularly suited for coupling write and erase voltages to a nonvolatile memory array while integrated on a common chip with the array. In one form, the circuit includes a two-phase pump, which upon being enabled draws a transient current from the high voltage input line and raises the voltage level on an internal capacitive node in closed loop fashion by effecting unidirectional transfers of charge between successive capacitive nodes. The elevated internal voltage provides a driving signal to a driving circuit which passes the high voltage on the input line to an output line without incurring threshold voltage losses.