Abstract: An apparatus includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an interface configured to send first data to be stored to the non-volatile memory. The controller further includes a control circuit configured to generate updated control information based on storing of the first data to the non-volatile memory. The interface is further configured to concurrently send second data and the updated control information to be stored at the non-volatile memory.

Abstract: An apparatus includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an interface configured to send first data to be stored to the non-volatile memory. The controller further includes a control circuit configured to generate updated control information based on storing of the first data to the non-volatile memory. The interface is further configured to concurrently send second data and the updated control information to be stored at the non-volatile memory.

Abstract: Systems and methods for managing regular maintenance operations in combination with infrequent extended maintenance operations in a non-volatile memory are disclosed. The method may include executing portions of the extended maintenance over the course of multiple regular maintenance operations. A memory system may include non-volatile memory and a controller configured to execute one or more of the steps of selecting a previously programmed source block for an extended maintenance operation, sequentially selecting a plurality of previously programmed blocks for regular maintenance operations and dividing execution of the extended maintenance operation up such that the extended maintenance operation is completed in parts across the plurality of regular maintenance operations.

Abstract: An apparatus includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an interface configured to send first data to be stored to the non-volatile memory. The controller further includes a control circuit configured to generate updated control information based on storing of the first data to the non-volatile memory. The interface is further configured to concurrently send second data and the updated control information to be stored at the non-volatile memory. The non-volatile memory is configured to store the second data and the updated control information in a non-blocking manner.

Abstract: A method is disclosed for only permitting data from a host to be written to a first non-volatile memory layer and only permitting data to be written into a second non-volatile memory layer via a maintenance operation over a single data path between the layers. The single data path may be an on-chip copy data path. A memory system includes a multi-layer non-volatile memory and data management circuitry, where the data management circuitry includes data flow path circuitry defining only a single data path for programming any data into the second layer. Maintenance manager circuitry and programming interleave circuitry in the data management circuitry are configured to select a maintenance schedule, and to interleave programming of host data with maintenance operation writes for the selected maintenance schedule only along the one or more data paths defined by the data flow path circuitry.

Abstract: A method is disclosed for only permitting data from a host to be written to a first non-volatile memory layer and only permitting data to be written into a second non-volatile memory layer via a maintenance operation over a single data path between the layers. The single data path may be an on-chip copy data path. A memory system includes a multi-layer non-volatile memory and data management circuitry, where the data management circuitry includes data flow path circuitry defining only a single data path for programming any data into the second layer. Maintenance manager circuitry and programming interleave circuitry in the data management circuitry are configured to select a maintenance schedule, and to interleave programming of host data with maintenance operation writes for the selected maintenance schedule only along the one or more data paths defined by the data flow path circuitry.

Abstract: Systems and methods for managing programming schedules of programming host data and maintenance operations in a non-volatile memory are disclosed. Foreground maintenance schedule cycles combining host data programming and maintenance operations are described to balance free space generation and consumption in a given non-volatile memory die of a memory system. A memory system may include non-volatile memory and a controller configured to execute one or more of the steps of selecting a non-volatile memory die in the non-volatile memory, identifying a foreground maintenance schedule type based on the selected die status, and selecting a source block in the selected die for executing the selected maintenance schedule type. The memory system interleaves the moving of valid data from the source block with host data writes to achieve a balance of free space generation and consumption.

Abstract: Systems and methods for managing regular maintenance operations in combination with infrequent extended maintenance operations in a non-volatile memory are disclosed. The method may include executing portions of the extended maintenance over the course of multiple regular maintenance operations. A memory system may include non-volatile memory and a controller configured to execute one or more of the steps of selecting a previously programmed source block for an extended maintenance operation, sequentially selecting a plurality of previously programmed blocks for regular maintenance operations and dividing execution of the extended maintenance operation up such that the extended maintenance operation is completed in parts across the plurality of regular maintenance operations.

Abstract: Memory systems having a volatile memory, a non-volatile memory arranged in blocks, and a controller coupled to the volatile memory and to the non-volatile memory. The controller is configured to maintain, in the volatile memory, a list of addresses of erased blocks of the non-volatile memory. The list of addresses of erased blocks of the non-volatile memory is limited to a maximum number of list entries. The controller is further configured to transfer the list of addresses of erased blocks of the non-volatile memory from the volatile memory to the non-volatile memory in response to the list containing its maximum number of list entries and/or in response to an operation that would increase the number of list entries to a number equal to or greater than the maximum number of list entries.

Abstract: A method and system for wear balancing in a flash memory device using bit error probability is disclosed. The flash memory device includes blocks with different life spans, leading potentially to one block wearing out before the other. In order to avoid this, a controller is configured to determine a bit error probability of a block and determine, based on the bit error probability, whether to select the block for storage of data. A method and system for selecting a block in a flash memory device based on the type of data is disclosed. The type of data may comprise flash management data (which may be used to manage the flash memory device) and host data. An indication of age associated with the block (such as bit error probability) is analyzed in order to determine whether to store the data in the block based on the type of data.

Abstract: A non-volatile memory organized into flash erasable blocks sorts units of data according to a temperature assigned to each unit of data, where a higher temperature indicates a higher probability that the unit of data will suffer subsequent rewrites due to garbage collection operations. The units of data either come from a host write or from a relocation operation. The data are sorted either for storing into different storage portions, such as SLC and MLC, or into different operating streams, depending on their temperatures. This allows data of similar temperature to be dealt with in a manner appropriate for its temperature in order to minimize rewrites. Examples of a unit of data include a logical group and a block.

Abstract: A non-volatile memory organized into flash erasable blocks sorts units of data according to a temperature assigned to each unit of data, where a higher temperature indicates a higher probability that the unit of data will suffer subsequent rewrites due to garbage collection operations. The units of data either come from a host write or from a relocation operation. Among the units more likely to suffer subsequent rewrites, a smaller subset of data super-hot is determined. These super-hot data are then maintained in a dedicated portion of the memory, such as a resident binary zone in a memory system with both binary and MLC portions.

Abstract: A data storage device includes a non-volatile memory and a controller. A method includes determining a decoding error associated with information stored at a page of a first block of the non-volatile memory. In response to the decoding error, a physical address is accessed from the management table. The physical address corresponds to a trial logical address. In response to the physical address corresponding to the page, the method further includes moving data from the page to a second block of the non-volatile memory.

Abstract: A system and method for coalescing data fragments in a volatile memory such as RAM cache is disclosed. The method may include storing multiple data fragments in volatile memory and initiating a single write operation to flash memory only when a predetermined number of data fragments have been received and aggregated into a single flash write command. The method may also include generating a binary cache index delta that aggregates in a single entry all of the binary cache index information for the aggregated data fragments. A memory system having a non-volatile memory, a volatile memory sized to at least store a number of data fragments equal to a physical page managed in a binary cache of the non-volatile memory, and a controller is disclosed. The controller may be configured to execute the method of coalescing data fragments into a single flash write operation described above.

Abstract: Memory systems having a volatile memory, a non-volatile memory arranged in blocks, and a controller coupled to the volatile memory and to the non-volatile memory. The controller is configured to maintain, in the volatile memory, a list of addresses of erased blocks of the non-volatile memory. The list of addresses of erased blocks of the non-volatile memory is limited to a maximum number of list entries. The controller is further configured to transfer the list of addresses of erased blocks of the non-volatile memory from the volatile memory to the non-volatile memory in response to the list containing its maximum number of list entries and/or in response to an operation that would increase the number of list entries to a number equal to or greater than the maximum number of list entries.

Abstract: A method and system for wear balancing in a flash memory device using bit error probability is disclosed. The flash memory device includes blocks with different life spans, leading potentially to one block wearing out before the other. In order to avoid this, a controller is configured to determine a bit error probability of a block and determine, based on the bit error probability, whether to select the block for storage of data. A method and system for selecting a block in a flash memory device based on the type of data is disclosed. The type of data may comprise flash management data (which may be used to manage the flash memory device) and host data. An indication of age associated with the block (such as bit error probability) is analyzed in order to determine whether to store the data in the block based on the type of data.

Abstract: A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. Decisions to archive data from the cache memory to the main memory depend on the attributes of the data to be archived, the state of the blocks in the main memory portion and the state of the blocks in the cache portion.

Abstract: A non-volatile memory system that has multiple memory banks initially assigns logical addresses to memory banks according to an assignment scheme, maintains this assignment for a period of time, then identifies frequently-written data (“hot-data”) assigned to a memory bank that is heavily worn over that period of time and reassigns it to a less worn memory bank.

Abstract: A method and system for managing maintenance operations in a multi-bank non-volatile storage device is disclosed. The method includes receiving a data write command and associated data from a host system for storage in the non-volatile storage device and directing a head of the data write command to a first bank in the and a tail of the data write command to a second bank, where the head of the data write command only includes data having logical block addresses preceding logical block addresses of data in the tail of the data write command. When a status of the first bank delays execution of the data write command the controller executes a second bank maintenance procedure in the second bank while the data write command directed to the first and second banks is pending. The system includes a plurality of banks, where each bank may be associated with the same or different controllers, and the one or more controllers are adapted to execute the method noted above.

Abstract: A non-volatile memory system that has multiple memory banks initially assigns logical addresses to memory banks according to an assignment scheme, maintains this assignment for a period of time, then identifies frequently-written data (“hot-data”) assigned to a memory bank that is heavily worn over that period of time and reassigns it to a less worn memory bank.