Patents by Inventor Alan G. Wood

Alan G. Wood has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7791184
    Abstract: A semiconductor package such as an image sensor package. A frame structure includes an array of frames, each having an aperture therethrough, into which an image sensor die in combination with a cover glass, filter, lens or other components may be installed in precise mutual alignment. Singulated image sensor dice and other components may be picked and placed into each frame of the frame structure. Alternatively, the frame structure may be configured to be aligned with and joined to a wafer bearing a plurality of image sensor dice, wherein optional, downwardly protruding skirts along peripheries of the frames may be received into kerfs cut along streets between die locations on the wafer, followed by installation of other package components. In either instance, the frame structure in combination with singulated image sensor dice or a joined wafer is singulated into individual image sensor packages. Various external connection approaches may be used.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: September 7, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Kyle K. Kirby, Warren M. Farnworth, Salman Akram
  • Patent number: 7786605
    Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate. A method for fabricating a semiconductor component with a through wire interconnect includes the steps of providing a semiconductor substrate with a substrate contact, forming a via through the substrate contact and part way through the substrate, placing the wire in the via, bonding the wire to the substrate contact, and then thinning the substrate from a second side to expose a contact on the wire.
    Type: Grant
    Filed: September 23, 2007
    Date of Patent: August 31, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, David R. Hembree
  • Patent number: 7776647
    Abstract: A semiconductor component includes a thinned semiconductor substrate having protective polymer layers on up to six surfaces. The component also includes contacts on a circuit side of the substrate, conductive vias in electrical contact with the contacts, and conductors on a backside of the substrate. A method for fabricating the component includes the steps of providing the semiconductor substrate with the contacts on the circuit side, forming conductive vias from the back side in electrical contact with the contacts, and forming conductors on the backside.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: August 17, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood, Trung Tri Doan
  • Patent number: 7768096
    Abstract: A system for fabricating semiconductor components includes a semiconductor substrate, a thinning system for thinning the semiconductor substrate, an etching system for forming the substrate opening, and a bonding system for bonding the conductive interconnect to the substrate contact. The semiconductor component can be used to form module components, underfilled components, stacked components, and image sensor semiconductor components.
    Type: Grant
    Filed: May 3, 2008
    Date of Patent: August 3, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, William M. Hiatt, David R. Hembree
  • Publication number: 20100144139
    Abstract: A backside method for fabricating a semiconductor component with a conductive interconnect includes the step of providing a semiconductor substrate having a circuit side, a backside, and a substrate contact on the circuit side. The method also includes the steps of forming a substrate opening from the backside to the substrate contact, and then bonding the conductive interconnect to an inner surface of the substrate contact.
    Type: Application
    Filed: February 10, 2010
    Publication date: June 10, 2010
    Inventors: Alan G. Wood, William M. Hiatt, David R. Hembree
  • Patent number: 7727872
    Abstract: A system for fabricating semiconductor components includes a semiconductor substrate, a thinning system for thinning the semiconductor substrate, an etching system for forming the substrate opening, and a bonding system for bonding the conductive interconnect to the substrate contact. The semiconductor component can be used to form module components, underfilled components, stacked components, and image sensor semiconductor components.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: June 1, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, William M. Hiatt, David R. Hembree
  • Patent number: 7723741
    Abstract: Methods of packaging microelectronic imagers and packaged microelectronic imagers. An embodiment of such a method can include providing an imager workpiece having a plurality of imager dies arranged in a die pattern and providing a cover substrate through which a desired radiation can propagate. The imager dies include image sensors and integrated circuitry coupled to the image sensors. The method further includes providing a spacer having a web that includes an adhesive and has openings arranged to be aligned with the image sensors. For example, the web can be a film having an adhesive coating, or the web itself can be a layer of adhesive. The method continues by assembling the imager workpiece with the cover substrate such that (a) the spacer is between the imager workpiece and the cover substrate, and (b) the openings are aligned with the image sensors. The attached web is not cured after the imager workpiece and the cover substrate have both been adhered to the web.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: May 25, 2010
    Assignee: Aptina Imaging Corporation
    Inventors: Warren M. Farnworth, Alan G. Wood, James M. Wark, David R. Hembree, Rickie C. Lake
  • Patent number: 7713841
    Abstract: A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor substrate includes a portion which extends substantially along and around an outer periphery of the semiconductor substrate to impart the thinned semiconductor substrate with rigidity. The support structure may be configured as a ring or as a member which substantially covers an active surface of the semiconductor substrate and forms a protective structure over each semiconductor device carried by the active surface. Assemblies that include the support structure and a semiconductor substrate are also within the scope of the present invention, as are methods for forming the support structures and thinning and post-thinning processes that include use of the support structures.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: May 11, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Warren M. Farnworth, David R. Hembree, Sidney B. Rigg, William M. Hiatt, Peter Benson, Kyle K. Kirby, Salman Akram
  • Patent number: 7709776
    Abstract: Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: May 4, 2010
    Assignee: Aptina Imaging Corporation
    Inventors: Warren M. Farnworth, Sidney B. Rigg, William Mark Hiatt, Alan G. Wood, Peter A. Benson, James M. Wark, David R. Hembree, Kyle K. Kirby, Charles M. Watkins, Salman Akram
  • Patent number: 7683458
    Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: March 23, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Charles M. Watkins, William M. Hiatt, David R. Hembree, James M. Wark, Warren M. Farnworth, Mark E. Tuttle, Sidney B. Rigg, Steven D. Oliver, Kyle K. Kirby, Alan G. Wood, Lu Velicky
  • Publication number: 20100047934
    Abstract: A method for fabricating a semiconductor component with an encapsulated through wire interconnect includes the steps of providing a substrate having a first side, a second side and a substrate contact; forming a via in the substrate contact and the substrate to the second side; placing a wire in the via; forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and forming a polymer layer on the first side leaving the first contact exposed. The polymer layer can be formed using a film assisted molding process including the steps of: forming a mold film on tip portions of the bonding members, molding the polymer layer, and then removing the mold film to expose the tip portions of the bonding members. The through wire interconnect provides a multi level interconnect having contacts on opposing sides of the semiconductor substrate.
    Type: Application
    Filed: October 19, 2009
    Publication date: February 25, 2010
    Inventors: David R. Hembree, Alan G. Wood
  • Patent number: 7663096
    Abstract: Microelectronic imaging devices and associated methods for attaching transmissive elements are disclosed. A manufacturing method in accordance with one embodiment of the invention includes providing an imager workpiece having multiple image sensor dies configured to detect energy over a target frequency. The image sensor dies can include an image sensor and a corresponding lens device positioned proximate to the image sensor. The method can further include positioning standoffs adjacent to the lens devices while the image sensor dies are connected to each other via the imager workpiece. At least one transmissive element can be attached to the workpiece at least proximate to the standoffs so the lens devices are positioned between the corresponding image sensors and the at least one transmissive element. Accordingly, the at least one transmissive element can protect the image sensors while the image sensor dies are still connected.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: February 16, 2010
    Assignee: Aptina Imaging Corporation
    Inventors: Warren M. Farnworth, Alan G. Wood
  • Patent number: 7659612
    Abstract: A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) attached to the substrate contact. The through wire interconnect provides a multi level interconnect having contacts on opposing first and second sides of the semiconductor substrate. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via having a bonded connection with the substrate contact, a first contact on the wire proximate to the first side, and a second contact on the wire proximate to the second side. The through wire interconnect (TWI) also includes a polymer layer which partially encapsulates the through wire interconnect (TWI) while leaving the first contact exposed. The semiconductor component can be used to fabricate stacked systems, module systems and test systems. A method for fabricating the semiconductor component can include a film assisted molding process for forming the polymer layer.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: February 9, 2010
    Assignee: Micron Technology, Inc.
    Inventors: David R. Hembree, Alan G. Wood
  • Patent number: 7645635
    Abstract: A semiconductor package such as an image sensor package, and methods for fabrication. A frame structure includes an array of frames, each having an aperture therethrough, into which an image sensor die in combination with a cover glass, filter, lens or other components may be installed in precise mutual alignment. Singulated image sensor dice and other components may be picked and placed into each frame of the frame structure. Alternatively, the frame structure may be configured to be aligned with and joined to a wafer bearing a plurality of image sensor dice, wherein optional, downwardly protruding skirts along peripheries of the frames may be received into kerfs cut along streets between die locations on the wafer, followed by installation of other package components. In either instance, the frame structure in combination with singulated image sensor dice or a joined wafer is singulated into individual image sensor packages. Various external connection approaches may be used for the packages.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: January 12, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Kyle K. Kirby, Warren M. Farnworth, Salman Akram
  • Patent number: 7598167
    Abstract: Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a partial via from the active surface through a conductive element thereon and a portion of the semiconductor substrate underlying the conductive element. The through via may then be completed by laser ablation or drilling from the back surface. In another embodiment, a partial via may be formed by laser ablation or drilling from the back surface of a semiconductor substrate to a predetermined distance therein. The through via may be completed from the active surface by forming a partial via extending through the conductive element and the underlying semiconductor substrate to intersect the laser-drilled partial via. In another embodiment, a partial via may first be formed by ablation or drilling from the back surface of the semiconductor substrate followed by dry etching to complete the through via and expose the underside of the conductive element.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: October 6, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Charles M. Watkins, Kyle K. Kirby, Alan G. Wood, Salman Akram, Warren M. Farnworth
  • Publication number: 20090243012
    Abstract: A microelectronic device assembly with an integrated conductive shield is disclosed herein. The microelectronic device assembly includes a semiconductor substrate, an integrated circuit carried by the semiconductor substrate, a dielectric encapsulant encasing at least a portion of the semiconductor substrate. The microelectronic device assembly also includes a conductive shield in direct contact with at least a portion of the dielectric encapsulant and an interconnect extending through the semiconductor substrate and in direct contact with the conductive shield.
    Type: Application
    Filed: March 28, 2008
    Publication date: October 1, 2009
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Kiran Kumar Vanam, Derek J. Gochnour, Alan G. Wood, James M. Derderian, Luke G. England, Owen R. Fay
  • Publication number: 20090243051
    Abstract: Microelectronic device assemblies having integrated conductive shields are disclosed herein. The microelectronic device assemblies include a semiconductor substrate having a bond site and a solder ball electrically connected to the bond site, a dielectric sidewall at least partially encapsulating the semiconductor substrate, and a conductive shield in direct contact with the sidewall and in electrical communication with the solder ball and the bond site.
    Type: Application
    Filed: March 28, 2008
    Publication date: October 1, 2009
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Kiran Kumar Vanam, Alan G. Wood, James M. Derderian, Derek J. Gochnour, Owen R. Fay, Luke G. England
  • Patent number: 7591069
    Abstract: Methods and apparatuses for bonding solder balls to bond pads are described. In one embodiment, portions of a plurality of solder balls are placed within a frame and in registered alignment with individual bond pads over a substrate. While the ball portions are within the frame, the balls are exposed to bonding conditions effective to bond the balls with their associated bond pads. In another embodiment, a frame is provided having a plurality of holes sized to receive individual solder balls. Individual balls are delivered into the holes from over the frame. The balls are placed into registered alignment with a plurality of individual bond pads over a substrate while the balls are in the holes. The balls are bonded with the individual associated bond pads.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: September 22, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood
  • Patent number: 7589010
    Abstract: Methods of manufacturing semiconductor devices using permanent or temporary polymer layers having apertures to expose contact pads and cover the active surfaces of the semiconductor devices.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: September 15, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood, James M. Wark, David R. Hembree, Syed Sajid Ahmad, Michael E. Hess, John O. Jacobson
  • Patent number: 7589406
    Abstract: A semiconductor component includes a carrier and multiple semiconductor substrates stacked and interconnected on the carrier. The carrier includes conductive members bonded to corresponding conductive openings on the semiconductor substrates. The component can also include terminal contacts on the carrier in electrical communication with the conductive members, and an outer member for protecting the semiconductor substrates. A method for fabricating the component includes the steps of providing the carrier with the conductive members, and providing the semiconductor substrates with the conductive openings. The method also includes the step of aligning and placing the conductive openings on the conductive members, and then bonding the conductive members to the conductive openings.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: September 15, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Alan G. Wood