Abstract: Disclosed herein are display systems and techniques for operating a display in a display system. An output image is formed by scanning a column of light emitters such that emitters in different rows of the column contribute to a same location in the output image. The emitters are driven using pulse-width modulation (PWM). PWM pulses are applied in synchronization with the scanning to cause emitters to emit light at an intensity corresponding to an illumination parameter. The driving includes generating, based on an illumination parameter, a PWM pulse by applying an analog signal in combination with applying a digital signal. The analog signal controls an amplitude of the PWM pulse. The digital signal controls a duration of the PWM pulse.

Abstract: Disclosed herein are display systems and techniques for operating a display in a display system. An output image is formed by scanning a column of light emitters such that emitters in different rows of the column contribute to a same location in the output image. The emitters are driven using pulse-width modulation (PWM). PWM pulses are applied in synchronization with the scanning to cause emitters to emit light at an intensity corresponding to an illumination parameter. The driving includes generating, based on an illumination parameter, a PWM pulse by applying an analog signal in combination with applying a digital signal. The analog signal controls an amplitude of the PWM pulse. The digital signal controls a duration of the PWM pulse.

Abstract: A method for estimating costs associated with relocating a plurality of items is provided. An interface is provided to a device. The interface receives user input data associated with relocating a plurality of items and displays a plurality of cost estimates that includes a total moving cost. The plurality of cost estimates are based at least in part on predefined item cost and user input data. At least one of the plurality of cost estimates is dynamically updated after at least a portion of the user input data is received. At least one of an estimate sheet and moving tariff form is provided. The estimate sheet is based at least in part on the plurality of cost estimates and received user input data. The moving tariff form provides a list of at least one charge and service associated with the plurality of cost estimates.

Abstract: A method is provided. User input data corresponding relocating a plurality of items is received at a user interface. An initial cost for the moving company to relocate the plurality of items is determined. Availability data is requested. The availability data indicates whether moving resources of the moving company are available for use during a time frame for relocating the plurality of items. Resource utilization of moving resources of the moving company during the time frame is determined based at least in part on the availability data. A determination is made whether the resource utilization meets a predefined threshold. The initial cost is modified based on whether the resource utilization meets the predefined threshold. A determination is made whether the user accepted the modified initial cost. The relocation of the plurality of items is scheduled by reserving at least some of the moving resources during the time frame.

Abstract: A method for estimating costs associated with relocating a plurality of items is provided. An interface is provided to a device. The interface receives user input data associated with relocating a plurality of items and displays a plurality of cost estimates that includes a total moving cost. The plurality of cost estimates are based at least in part on predefined item cost and user input data. At least one of the plurality of cost estimates is dynamically updated after at least a portion of the user input data is received. At least one of an estimate sheet and moving tariff form is provided. The estimate sheet is based at least in part on the plurality of cost estimates and received user input data. The moving tariff form provides a list of at least one charge and service associated with the plurality of cost estimates.

Abstract: A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.

Abstract: A service station is provided with a plurality of vehicle servicing islands including liquid fuel blending pumps for dispensing and blending fuel components from underground tanks for refueling standard gasoline engine driven vehicles, standard diesel engine vehicles, vehicles with engines requiring dual fuels, vehicles with HCCI engines requiring low octane gasoline blended with standard diesel fuel, and fuel cell powered vehicles having onboard reformers. Other service islands include pumps for dispensing compressed hydrogen to fuel cell powered vehicles that do not include onboard reformers. In addition, service islands are provided for recharging the batteries of pure electric powered vehicles.

Abstract: An integrated circuit memory device comprises a memory array to store data, a circuit to output the data at a pin, and a register to store a value that indicates a mode of operation of the integrated circuit memory device. The mode of operation is selected from at least one of a synchronous mode of operation and an asynchronous mode of operation. During the synchronous mode of operation, the circuit outputs the data in response to a transition of an external clock signal. During the asynchronous mode of operation, the circuit outputs the data after a period of time from when a transition of an external control signal is detected.

Abstract: An integrated circuit memory device comprises a latch circuit to load an address using a first control signal. A first signal level transition of the first control signal is used to load the address. A memory array stores data at a memory location that is based on the address. An output buffer outputs the data after a period of time from the first signal level transition. A register stores a value that specifies between at least a first mode and a second mode. When the value specifies the first mode, the output buffer outputs the data in response to address transitions that occur after the first signal level transition. When the value specifies the second mode, the output buffer outputs data synchronously with respect to an external clock signal.

Abstract: A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.

Abstract: A method of generating and verifying a memory test is disclosed. A simulator is used to verify that the sequence of time-ordered commands complies with a set of operating constraints for the memory. A packer may thereafter be used to optimize run time of the verified test.

Abstract: A method of generating and verifying a memory test is disclosed. A simulator is used to verify that the sequence of time-ordered commands complies with a set of operating constraints for the memory. A packer may thereafter be used to optimize run time of the verified test.

Abstract: A method of generating and verifying a memory test is disclosed. A simulator is used to verify that the sequence of time-ordered commands complies with a set of operating constraints for the memory. A packer may thereafter be used to optimize run time of the verified test.

Abstract: A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.

Abstract: A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.

Abstract: A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.

Abstract: A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.

Abstract: A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.

Abstract: A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.

Abstract: A high speed bus system in which at least one master device, such as a processor and at least one DRAM slave device are coupled to the bus. An innovative packet format and device interface which utilizes a plurality of time and space saving features in order to decrease the die size of the device receiver and decrease the overall latency on the bus is provided. In the preferred embodiment the request packet is transmitted on ten multiplexed transmission lines, identified as BusCtl and BusData. The packet is transmitted over six sequential bus cycles, wherein during each bus cycle, a different portion of the packet is transmitted. The lower order address bits are moved ahead of the higher order address bits of the memory request. This enables the receiving device to process the memory request faster as the locality of the memory reference with respect to previous references can be immediately determined and page mode accesses on the DRAM can be initiated as quickly as possible.