Abstract: Vector shifting elements of a vector register by varying amounts in a single process is achieved in a vector supercomputer processor. A first vector register contains a set of operands, and a second vector register contains a set of shift counts, one shift count for each operand. Operands and shift counts are successively transferred to a vector shift functional unit, which shifts the operand by an amount equal to the value of the shift count. The shifted operands are stored in a third vector register. The vector shift functional unit also achieves word shifting of a predetermined number of vector register elements to different word locations of another vector register.

Abstract: In a tightly coupled communication scheme based on a common shared resource circuit having a plurality of shared information registers and adapted particularly to a multiprocessing system having 2.sup.N CPUs, a method of performing a read-and-modify instruction. Data stored in a shared information register is read from the shared register, captured in a read and increment circuit and sent to the processor issuing the read-and-modify instruction. At the same time, a mathematical function is performed on the captured data is incremented and the result is written back into the shared information register.

Abstract: Vector shifting elements of a vector register by varying amounts in a single process is achieved in a vector supercomputer processor. A first vector register contains a set of operands, and a second vector register contains a set of shift counts, one shift count for each operand. Operands and shift counts are successively transferred to a vector shift functional unit, which shifts the operand by an amount equal to the value of the shift count. The shifted operands are stored in a third vector register. The vector shift functional unit also achieves word shifting of a predetermined number of vector register elements to different word locations of another vector register.

Abstract: A system for interprocessor communication including a shared register resource accessible by any one of the processors through the using internal communication paths. The shared register resource is distributed among the processors with each processor including a portion of the total system resource. Each processor includes an access circuit for receiving instructions from the CPU and generating control bytes to be distributed to the shared register resource circuits in each of the processors, which use the control byte to control shared resource access. Each shared register resource circuit is capable of controlling the I/O channels associated with its respective processor. A local access circuit for each CPU is capable of obtaining access to and controlling any of the I/O channels in the system via the shared register resource circuits.

Abstract: Vector shifting elements of a vector register by varying amounts in a single process is achieved in a vector supercomputer processor. A first vector register contains a set of operands, and a second vector register contains a set of shift counts, one shift count for each operand. Operands and shift counts are successively transferred to a vector shift functional unit, which shifts the operand by an amount equal to the value of the shift count. The shifted operands are stored in a third vector register. The vector shift functional unit also achieves word shifting of a predetermined number of vector register elements to different word locations of another vector register.

Abstract: A tightly coupled interprocessor communication system based on a common shared resource circuit and adapted particularly to a multiprocessing system including 2.sup.N processors. A local control circuit is connected to each processor and a shared resource circuit is tightly coupled through the local control circuits to each processor. The shared resource circuit includes a shared semaphore register, a shared information register and a read and increment circuit which can be used to increment the contents of a shared information register as a single instruction. The local control circuit includes an issue control circuit used to determine when a transaction with the shared resource circuit is permitted, a circuit which generates a command to the shared resource circuit when the transaction is permitted and a real time clock.

Abstract: The present invention provides a vector processing computer system adapted for real-time I/O. The present invention combines a rotating priority interrupt scheme, dedicated real-time interrupt lines for each processor, and access to privileged communication/control modes of operation for processors operating in real-time to create a flexible hardware design adaptable for use in many different real-time applications.

Abstract: A method of implementing a privileged instruction that enables the development of new operating systems in user mode. The instruction decode logic includes a maskable interrupt generator that interrupts the processor during the processing of privileged instructions in user mode. An exception handler processes the privileged instruction interrupt and performs a function similar to the execution of the privileged instruction in privileged instruction mode. The combination of the privileged instruction interrupt and the post-interrupt exception handling enables the operating system developer to test new operating systems by laying them over the current operating system.

Abstract: In a tightly coupled communication scheme based on a common shared resource circuit and adapted particularly to a multiprocessing system having 2.sup.N CPUs, a method of accessing data in a shared resource register. An instruction issue circuit reads a semaphore bit in a local control circuit. If the bit is clear, the next instruction issues. If, however, the bit is set, a branch is taken and instructions are executed starting at the branch address.

Abstract: The present invention provides a memory interface system wherein there is provided a memory having multiple ports and divided into sections, with each section divided into subsections, with memory banks within each subsection, and the banks divided into at least two bank groups. The invention further provided a memory interface for controlling the referencing of said memory banks according to which bank group they are in.

Abstract: A method of memory access for sharing a memory between multiple processors. The memory comprises a plurality of sections and each section is connected to each processor by a memory path. Each section includes a plurality of subsections and each subsection includes a plurality of banks which includes a plurality of individually addressable memory locations. Memory references attempting to access the individually addressable memory locations are generated by the processors. Subsection conflicts between the memory references generated by a plurality of ports of each processor are resolved so that only one of the memory references from each processor is allowed to access one of the plurality of subsections at a time. Section conflicts between the memory references generated by the plurality of ports of each processor are resolved so that only one of the plurality of ports of each processor connects by the memory path for each processor to one of the plurality of the sections at a time.

Abstract: A method and apparatus provides bit manipulation of data in vector registers of a vector register computer system. Matrix multiplication is accomplished at a bit level of data stored as two matrices in a vector computer system to produce a matrix result. The matrices may be at least as large as 64 bits by 64 bits and multiplied by another 64 by 64 matrix by means of a vector matrix multiplication functional unit operating on the matrices within a vector processor. The resulting data is also stored at a 64 bit by 64 bit matrix residing in a resultant vector register.

Abstract: A computer system shares memory between multiple processors by dividing the memory into a plurality of sections, subsections, and banks, and by providing a memory path between each processor and each section of memory. Each processor may generate references to the memory from any one of four ports, which are multiplexed to the memory paths and onto the sections of memory. The system provides that each processor has an associated register in each subsection of memory and that each processor can make no more than one reference to a subsection at a time. Reference conflict resolution means are provided at the processor level to arbitrate conflicts between ports in the processors attempting to reference the same section or subsection in the memory. Reference conflict resolution means are provided at the subsection level of the memory to arbitrate conflicts between different processors attempting to reference the same banks of memory.

Abstract: A multiprocessing system and method for multiprocessing is disclosed. A pair of processors are provided, and each are connected to a central memory through a plurality of memory reference ports. The processors are further each connected to a plurality of shared registers which may be directly addressed by either processor at rates commensurate with intra-processor operation. The shared registers include registers for holding scalar and address information and registers for holding information to be used in coordinating the transfer of information through the shared registers. A multiport memory is provided and includes a conflict resolution circuit which senses and prioritizes conflicting references to the central memory. Each CPU is interfaced with the central memory through three ports, with each of the ports handling different ones of several different types of memory references which may be made.

Abstract: A memory interface and conflict resolution network for a multiprocessor system. The memory is multisectional and each section of memory has a plurality of individually addressable memory banks organized in an interleaved fashion and a section level conflict resolution network. Each processor in the system includes several ports and a gating network such that each port may access any section of memory, but access is restricted to no more than one reference per processor per clock period to each section of memory. References generated from different ports of the same processor are automatically synchronized. Each processor has a conflict resolution circuit to resolve conflicts between different ports seeking access to the same section of memory.

Abstract: A pair of processors are each connected to a central memory through a plurality of memory reference ports. The processors are further each connected to a plurality of shared registers which may be directly addressed by either processor at rates commensurate with intra-processor operation. The shared registers include registers for holding scalar and address information and registers for holding information to be used in coordinating the transfer of information through the shared registers. A multiport memory is provided and includes a conflict resolution circuit which senses and prioritizes conflicting references to the central memory. Each CPU is interfaced with the central memory through three ports, with each of the ports handling different ones of several different types of memory references which may be made. At least one I/O port is provided to be shared by the processors in transferring information between the central memory and peripheral storage devices.

Abstract: A multiprocessing system and method for multiprocessing is disclosed. A pair of processors are provided, and each are connected to a central memory through a plurality of memory reference ports. The processors are further each connected to the plurality of shared registers which may be directly addressed by either processor at rates commensurate with intraprocessor operation. The shared registers include registers for holding scalar and address information and registers for holding information to be used in coordinating the transfer of information through the shared registers. A multiport memory is provided and includes a conflict resolution circuit which senses and prioritizes conflicting references to the central memory. Each CPU is interfaced with the central memory through three ports, with each of the ports handling different ones of several different types of memory references which may be made.