Abstract: Example embodiments relate to response control for memory modules that include or interface with non-compliant memory technologies. A memory module may include an interface to a memory bus that complies with a data transfer standard, wherein the memory bus communicates with a memory controller, and an interface to a non-compliant memory technology that does not comply with the data transfer standard. The memory module may include a command monitoring circuit to determine whether a command from the memory controller has been or will be completed by the non-compliant memory circuit within a defined amount of time within which a command should be completed according to the data transfer standard. The memory module may include an error causing circuit that signals to the memory controller or an operating system when the command has not or will not complete within the defined amount of time.

Abstract: A power throttling method and system for a memory controller. In one embodiment, a throttle value and a counter for controlling memory accesses by the memory controller to one or more memory devices are provided in the memory controller. Responsive to a throttle control signal indicative of an over-current state, on each clock cycle, the value of the counter is incremented by one, the counter value is compared to the throttle value, and if the counter value is greater than the throttle value, issuance of a memory operation cycle during the clock cycle is prevented.