Abstract: A fault-tolerant code semiconductor memory storage device includes a array of individual multi-level storage devices arranged in a prescribed sequence. A controller is provided for programming the array with sequential data. The controller detects an occurrence of a faulty storage device in the array during a programming of the array with the sequential data. The controller further codes the occurrence of the faulty storage device in a subsequent storage device in the sequence of devices using a fault-tolerant code. A method of fault-tolerant coding of a semiconductor memory storage device is also disclosed.

Abstract: A distance sensor has a capacitive element in turn having a first capacitor plate which is positioned facing a second capacitor plate whose distance is to be measured. In the case of fingerprinting, the second capacitor plate is defined directly by the skin surface of the finger being printed. The sensor comprises an inverting amplifier, between the input and output of which the capacitive element is connected to form a negative feedback branch. By supplying an electric charge step to the input of the inverting amplifier, a voltage step directly proportional to the distance being measured is obtained at the output.

Abstract: A variable capacitor in a semiconductor device is described in which the capacitance is varied by the movement of a dielectric material in the space between the plates of the capacitor in response to an external stimulus. A method of making such a variable capacitor is also described in which the capacitor is built in a layered structure with the top layer including a portion of dielectric material extending into the space between the capacitor plates. After formation of the top layer, an intermediate layer is etched away to render the top layer flexible to facilitate movement of the dielectric material in the space between the capacitor plates.

Abstract: A memory device includes an array of floating gate FET memory cells capable of storing either analog or digital data. The memory device includes first read-write circuitry for storage and retrieval of digital data, and second read-write circuitry for storage and retrieval of analog data. As a result, the digital data storage capability facilitates real-time operation of devices using the memory device without sacrificing the memory capacity capabilities of analog data storage. When a host device using the memory device is not in use, the stored digital data may be read out from the memory device, converted to analog form and then stored in the memory device, re-capturing the data density capabilities of analog data storage in floating gate FET memory cells.

Abstract: An electronic device for performing convolution operations comprises shift registers for receiving binary input values representative of an original matrix, synapses for storing weights correlated with a mask matrix, and neurons for outputting a binary result dependent on the sum of the binary values weighted by the synapses. Each synapse has a conductance correlated with the weight stored and dependent upon the binary input value. Each neuron generates the binary result in dependence on the total conductance of the corresponding synapses.

Abstract: A neural network including a number of synaptic weighting elements, and a neuron stage; each of the synaptic weighting elements having a respective synaptic input connection supplied with a respective input signal; and the neuron stage having inputs connected to the synaptic weighting elements, and being connected to an output of the neural network supplying a digital output signal. The accumulated weighted inputs are represented as conductances, and a conductance-mode neuron is used to apply nonlinearity and produce an output. The synaptic weighting elements are formed by memory cells programmable to different threshold voltage levels, so that each presents a respective programmable conductance; and the neuron stage provides for measuring conductance on the basis of the current through the memory cells, and for generating a binary output signal on the basis of the total conductance of the synaptic elements.

Abstract: This invention relates to a voltage comparator with an input for an analog signal and an output for a digital signal, comprising an inverter which has an input coupled to the comparator input and an output coupled to the comparator output, and comprising at least two MOS transistors coupled to each other, at least one of the two MOS transistors being of the floating gate type.

Abstract: A planar, capacitive-type, rectangular, and multi-pixel fingerprint sensing array is mounted on the horizontal and generally rectangular top-surface of a dome that extends upward generally from the center of a horizontally disposed and generally rectangular silicon substrate member. The dome is formed by four upward extending and inclined, or tapered, side wall surfaces, at least one wall surface of which carries electrical circuit paths that electrically connected to the various circuit elements of the sensing array. A generally rectangular, encircling and wall-like card carrier assembly includes a generally horizontal upper-surface having a generally centered opening through which only the dome and sensing array project upward. The bottom-surface of the card carrier assembly is mounted to edge portions of the silicon substrate member in a manner to surround and protect all but the upward extending dome.

Abstract: The present invention relates to a digital-to-analog converter having a plurality of inputs for digital signals and an output for an analog signal. It comprises a current amplification circuit having an input and an output coupled to the converter output, and a plurality of floating gate MOS transistors corresponding to the plurality of converter inputs and having their source terminals coupled together and to a first reference of potential. The converter has drain terminals coupled together and to the input of the amplification circuit, and has control terminals coupleable, under control from the inputs of the plurality, to different references of potential having selected fixed values.

Abstract: A variable capacitor in a semiconductor device is described in which the capacitance is varied by the movement of a dielectric material in the space between the plates of the capacitor in response to an external stimulus. A method of making such a variable capacitor is also described in which the capacitor is built in a layered structure with the top layer including a portion of dielectric material extending into the space between the capacitor plates. After formation of the top layer, an intermediate layer is etched away to render the top layer flexible to facilitate movement of the dielectric material in the space between the capacitor plates.

Abstract: An input structure for associative memories, including an array of elementary cells, a number of input lines, a number of output lines, a number of address lines, and a number of enable lines. Each elementary cell is formed by a D flip-flop having a data input coupled to one of the address lines and an enable input coupled to one of the enable lines, and by a switch coupled between an input line and an output line, and having a control input coupled to the output of a respective latch to selectively couple the respective input line and output line according to the data stored in the latch.

Abstract: The present invention relates to a digital-to-analog converter having a plurality of inputs for digital signals, and an output for an analog signal. It also contains a charge integration circuit having an input and an output coupled to the converter output, and a plurality of floating gate MOS transistors corresponding to the plurality of converter inputs, the MOS transistors all having their source and drain terminals coupled together and to the input of the integration circuit, and having control terminals coupleable, under control from the plurality of inputs of digital signals, to different reference voltages having selected fixed values.

Abstract: The charge injection circuit of this invention comprises at least one pair of floating gate MOS transistors having source and drain terminals which are coupled together and to an injection node, and at least one corresponding pair of generators of substantially step-like voltage signals having an initial value and a final value, and having outputs respectively coupled to the control terminals of said transistors. The signal generators are such that the initial value of a first of the signals is substantially the equal of the final value of a second of the signals, and that the final value of the first signal is substantially the equal of the initial value of the second signal.

Abstract: The present invention relates to an analog voltage-signal selector device of the type comprising at least one plurality of comparator circuits operating in parallel and each having at least a first and second input terminals and designed to receive respectively an analog voltage-comparison signal and analog voltage signals of predetermined value and at least one output terminal for digital voltage signals. This selector device also comprises at least one logic circuit having a plurality of input terminals each connected to a corresponding output terminal of the comparator circuits and at least one output terminal. Finally the selector incorporates at least one plurality of latches each having at least one input terminal connected to the output terminal of a corresponding comparator circuit and at least one drive terminal coupled to the output terminal of the logic circuit with each of the memory circuits having at least one output terminal corresponding to an output of the selector.

Abstract: A programmable reference voltage source includes a nonvolatile memory cell, the floating-gate region of which stores electric charges determining a memorized threshold value. The drain terminal of the cell is biased at a constant voltage, and the source terminal is coupled to a constant-current source and to the inverting input of an operational amplifier having the noninverting input coupled to a reference voltage and the output coupled to the gate terminal of the cell. By defining the threshold of the cell as the gate voltage (measured with respect to ground) capable of causing the cell to be flown by the current set by the current source, the output voltage of the operational amplifier equals the threshold and may be used as a programmable reference in analog memories.

Abstract: To check the programming of a nonvolatile memory cell storing an actual threshold value, the drain terminal of the cell is biased at a constant voltage; the gate terminal is biased at a check voltage; the cell is supplied with a predetermined current to determine a gate-source voltage drop related to the actual threshold value; and the voltage at the source terminal is supplied to an input of an operational amplifier. In an open-loop configuration, the desired threshold value of the set predetermined current is supplied as the check voltage; the amplifier compares the source voltage with the ground; and switching of the amplifier indicates the desired threshold value has been reached. In a closed-loop configuration, the output of the operational amplifier is connected directly to the gate terminal of the cell, and supplies the desired threshold value directly.

Abstract: An isolated current shunt transducer includes a current shunt that produces a voltage difference between the current shunt's first and second ends, with the voltage difference being related to a current flowing through the current shunt. The transducer also includes an isolation barrier positioned between the current shunt and a processing circuit to isolate the processing circuit from a voltage that is common to both ends of the current shunt. Two or more transducers may be included in a power meter for measuring power delivered to a load by a multiple phase power distribution circuit. In such a power meter, a processing circuit is connected to the current shunts through the isolation barriers and is operable to produce multiple phase power measurements based on the differences between the voltages at the first and second ends of the current shunts.

Abstract: Non-volatile memory cell with double level of polycrystalline silicon has a source region (38), a drain region (31), a channel region (34) between said source and drain regions, a floating gate (33), and a control gate (32) in which the channel region area extends into two lateral zones beneath the two gates and perpendicular to the source-drain direction.

Abstract: A low power analog absolute differencing circuit and architecture is disclosed. The circuit includes an integrating amplifier with an input node connected to a common integration line. The common integration line is connected to a set of analog comparison circuits to form an analog vector absolute differencing circuit row. Each of the analog comparison circuits compares a first analog signal to a second analog signal to produce an absolute difference signal. The absolute difference signal from each analog comparison circuit is transmitted in the form of charge drawn from the common integration line. The integrating amplifier provides an integration sum corresponding to the sum of the absolute difference signals. The analog absolute differencing architecture includes a set of analog vector absolute differencing circuit rows arranged to form an analog absolute difference computing array. The analog absolute difference computing array is loaded with a data block input array and a data frame input array.

Abstract: A low power analog absolute differencing circuit includes an integrating amplifier with an input node connected to a common integration line. The common integration line is connected to a set of analog comparison circuits to form an analog vector absolute differencing circuit row. Each of the analog comparison circuits compares a first analog signal to a second analog signal to produce an absolute difference signal. The absolute difference signal from each analog comparison circuit is transmitted in the form of charge drawn from the common integration line. The integrating amplifier provides an integration sum corresponding to the sum of the absolute difference signals. The analog absolute differencing architecture includes a set of analog vector absolute differencing circuit rows arranged to form an analog absolute difference computing array. The analog absolute difference computing array is loaded with a data block input array and a data frame input array.