Abstract: A transceiver, a communication system and an associated method thereof for reducing overall power consumption and complexity of the transceiver that operates over short reach twisted pair cables. The analog front end (AFE) of the transceiver communicates over at least one twisted pair that is configured only for transmission of data streams and communicates over at least one twisted pair that is only for reception of data streams. The transceiver includes circuitry that generates multiplexed and demultiplexed data streams for communication with the analog front end. Additionally, the transceiver utilizes at least certain portions of signal processing circuitry and AFE of a 10 GBASE-T transceiver or the like.

Abstract: An apparatus for operating a low data-rate (LDR) link and legacy switch at a high data-rate (HDR) includes a first block and a second block. The first block receives input signals from the legacy switch and generates identical output signals. The second block receives the identical output signals and generates an HDR signal for communication over the LDR link coupled to an access point. Further, a media access control (MAC) interface communicates data at a first data rate with an Ethernet PHY block including a first-in-first-out (FIFO) module and a buffer. The FIFO receives data from the MAC interface at the first data rate and transmits data at a second data rate. The buffer receives data from the Ethernet port at the second data rate and transmits the received data at the first data rate in response to detection of an end of packet.

Abstract: Disclosed are method and system for Ethernet media conversion supporting high-speed wireless access points. The method includes receiving at each of a plurality of input-side Ethernet modules in a media converter, a plurality of input data streams at a first data rate. In the media converter each of the plurality of input data streams may be aggregated into an output data stream at a second data rate. The output data stream may then be transmitted at the second data rate from an output-side Ethernet module in the media converter. Each of the input data streams may be received from an Ethernet switch, and the output data stream may be transmitted to a wireless access point. In one exemplary implementation, each of the input-side Ethernet modules may include a 1G PHY, while the output-side Ethernet module may include one or both of a 2.5G PHY and a 4G PHY.

Abstract: A transceiver, a communication system and an associated method thereof for reducing overall power consumption and complexity of the transceiver that operates over short reach twisted pair cables. The analog front end (AFE) of the transceiver communicates over at least one twisted pair that is configured only for transmission of data streams and communicates over at least one twisted pair that is only for reception of data streams. The transceiver includes circuitry that generates multiplexed and demultiplexed data streams for communication with the analog front end. Additionally, the transceiver utilizes at least certain portions of signal processing circuitry and AFE of a 10 GBASE-T transceiver or the like.

Abstract: An apparatus for operating a low data-rate (LDR) link and legacy switch at a high data-rate (HDR) includes a first block and a second block. The first block receives input signals from the legacy switch and generates identical output signals. The second block receives the identical output signals and generates an HDR signal for communication over the LDR link coupled to an access point. Further, a media access control (MAC) interface communicates data at a first data rate with an Ethernet PHY block including a first-in-first-out (FIFO) module and a buffer. The FIFO receives data from the MAC interface at the first data rate and transmits data at a second data rate. The buffer receives data from the Ethernet port at the second data rate and transmits the received data at the first data rate in response to detection of an end of packet.

Abstract: Disclosed are method and system for Ethernet media conversion supporting high-speed wireless access points. The method includes receiving at each of a plurality of input-side Ethernet modules in a media converter, a plurality of input data streams at a first data rate. In the media converter each of the plurality of input data streams may be aggregated into an output data stream at a second data rate. The output data stream may then be transmitted at the second data rate from an output-side Ethernet module in the media converter. Each of the input data streams may be received from an Ethernet switch, and the output data stream may be transmitted to a wireless access point. In one exemplary implementation, each of the input-side Ethernet modules may include a 1G PHY, while the output-side Ethernet module may include one or both of a 2.5G PHY and a 4G PHY.

Abstract: Disclosed are method and system for Ethernet media conversion supporting high-speed wireless access points. The method includes receiving at each of a plurality of input-side Ethernet modules in a media converter, a plurality of input data streams at a first data rate. In the media converter each of the plurality of input data streams may be aggregated into an output data stream at a second data rate. The output data stream may then be transmitted at the second data rate from an output-side Ethernet module in the media converter. Each of the input data streams may be received from an Ethernet switch, and the output data stream may be transmitted to a wireless access point. In one exemplary implementation, each of the input-side Ethernet modules may include a 1G PHY, while the output-side Ethernet module may include one or both of a 2.5G PHY and a 4G PHY.

Abstract: In a satellite gateway, data is transmitted over a downstream channel at different throughput rates. Data destined for each subscriber/receiver is assigned a throughput rate depending upon the downstream signal quality of that subscriber/receiver. The downstream data is parsed to extract data packets. The data packets are then loaded into packet queues based on an identifier within such packets. The queues represent a bandwidth efficiency or throughput rate that can be currently tolerated by specific subscribers that may also be based on the current signal quality at a subscriber location. The parsed data traffic is processed based on the profile of the plurality of profiles to produce processed data traffic, and transmitted from the packet queues over a downstream channel.

Abstract: Disclosed are method and system for Ethernet media conversion supporting high-speed wireless access points. The method includes receiving at each of a plurality of input-side Ethernet modules in a media converter, a plurality of input data streams at a first data rate. In the media converter each of the plurality of input data streams may be aggregated into an output data stream at a second data rate. The output data stream may then be transmitted at the second data rate from an output-side Ethernet module in the media converter. Each of the input data streams may be received from an Ethernet switch, and the output data stream may be transmitted to a wireless access point. In one exemplary implementation, each of the input-side Ethernet modules may include a 1 G PHY, while the output-side Ethernet module may include one or both of a 2.5 G PHY and a 4 G PHY.

Abstract: In a satellite gateway, data is transmitted over a downstream channel at different throughput rates. Data destined for each subscriber/receiver is assigned a throughput rate depending upon the downstream signal quality of that subscriber/receiver. The downstream data is parsed to extract data packets. The data packets are then loaded into packet queues based on an identifier within such packets. The queues represent a bandwidth efficiency or throughput rate that can be currently tolerated by specific subscribers that may also be based on the current signal quality at a subscriber location. The parsed data traffic is processed based on the profile of the plurality of profiles to produce processed data traffic, and transmitted from the packet queues over a downstream channel.

Abstract: In a DOCSIS based satellite gateway data is transmitted over a single downstream channel, at different throughput rates. Data destined for each subscriber/receiver is assigned a throughput rate depending upon the downstream signal quality of that subscriber/receiver. To accomplish this, the downstream DOCSIS MAC data is parsed to extract DOCSIS packets. The DOCSIS packets are then loaded into packet queues based on an identifier within such packets such as the MAC destination address or SID. Each of the queues represents a bandwidth efficiency or throughput rate that can be currently tolerated by specific subscribers based on the current signal quality being experienced at the subscriber location. A PHY-MAP describing the downstream data structure to be transmitted and inserted into the downstream data. Data is extracted from the packet queues in queue blocks as defined by the PHY-MAP.

Abstract: Herein described are at least a method and a system for implementing a high speed Tomlinson-Harashima Precoder. The method comprises using an L-tap transpose configuration of a Tomlinson-Harashima Precoder and processing a first discrete time sampled sequence using said L coefficients and L state variables by clocking the L-tap Tomlinson-Harashima Precoder using a clock signal wherein the clock signal has a clock rate equal to one half the symbol rate of the discrete time sampled sequence. In a representative embodiment, an L-tap Tomlinson-Harashima Precoder comprises a single integrated circuit chip, wherein the integrated circuit chip comprises at least one circuitry for processing a discrete time sampled sequence using L coefficients and L state variables by way of clocking the discrete time sampled sequence using a clock signal having a clock rate that is one half the symbol rate of the discrete time sampled sequence.

Abstract: Methods and systems for modifying DOCSIS-based transmission paths for communication in higher frequency and/or wireless environments, such as wireless terrestrial communication systems and satellite communication systems. An inner turbo-code is combined with a DOCSIS based Reed-Solomon (“RS”) forward error correction (“FEC”) coding scheme, to produce a concatenated turbo-RS code (other FEC codes can be utilized). In phase and quadrature phase (“I-Q”) processing is utilized to enable relatively low cost up-converter implementations. The I-Q processing is preferably performed at baseband, essentially pre-compensating for analog variations in the transmit path. Power amplifier on/off control capable of controlling on/off RF power control of remote transmitters is modulated on a transmit cable to reduce the need for a separate cable.

Abstract: An integrated burst FSK receiver is provided to receive and interpret an RF signal using FSK modulation. The integrated burst FSK receiver uses a programmable RF local oscillator to mix a received signal down to an IF range or baseband, where it is filtered and sampled for subsequent digital processing. Digital filtering and detection are employed to improve overall bit error rate performance and receiver sensitivity. A programmable digital low-pass or band-pass filter can also be used to suppress interference. A matched filter correlator can be used for detection and symbol timing adjustment in one mode, while an adaptive frequency comparator can be used in another mode. Circuits are provided that estimate carrier offset, frequency deviation and signal strength. These measurements can then be used to optimize the receiver performance. A method for receiving and interpreting an RF signal using FSK modulation is also provided.

Abstract: Methods and systems for modifying DOCSIS-based transmission paths for communication in higher frequency and/or wireless environments, such as wireless terrestrial communication systems and satellite communication systems. An inner turbo-code is combined with a DOCSIS based Reed-Solomon (“RS”) forward error correction (“FEC”) coding scheme, to produce a concatenated turbo-RS code (other FEC codes can be utilized). In phase and quadrature phase (“I-Q”) processing is utilized to enable relatively low cost up-converter implementations. The I-Q processing is preferably performed at baseband, essentially pre-compensating for analog variations in the transmit path. Power amplifier on/off control capable of controlling on/off RF power control of remote transmitters is modulated on a transmit cable to reduce the need for a separate cable.

Abstract: Methods and systems for modifying DOCSIS-based transmission paths for communication in higher frequency and/or wireless environments, such as wireless terrestrial communication systems and satellite communication systems. An inner turbo-code is combined with a DOCSIS based Reed-Solomon (“RS”) forward error correction (“FEC”) coding scheme, to produce a concatenated turbo-RS code (other FEC codes can be utilized). In phase and quadrature phase (“I-Q”) processing is utilized to enable relatively low cost up-converter implementations. The I-Q processing is preferably performed at baseband, essentially pre-compensating for analog variations in the transmit path. Power amplifier on/off control capable of controlling on/off RF power control of remote transmitters is modulated on a transmit cable to reduce the need for a separate cable.

Abstract: In a DOCSIS based satellite gateway data is transmitted over a single downstream channel, at different throughput rates. Data destined for each subscriber/receiver is assigned a throughput rate depending upon the downstream signal quality of that subscriber/receiver. To accomplish this, the downstream DOCSIS MAC data is parsed to extract DOCSIS packets. The DOCSIS packets are then loaded into packet queues based on an identifier within such packets such as the MAC destination address or SID. Each of the queues represents a bandwidth efficiency or throughput rate that can be currently tolerated by specific subscribers based on the current signal quality being experienced at the subscriber location. A PHY-MAP describing the downstream data structure to be transmitted and inserted into the downstream data. Data is extracted from the packet queues in queue blocks as defined by the PHY-MAP.

Abstract: In an integrated satellite receiver, improved header acquisition techniques are described for quickly locating a header symbol sequence in a data stream substantially implemented on a single CMOS integrated circuit. To identify the location of a header symbol sequence in a data stream, a selected header acquisition technique employs a real time correlator followed by an accumulator. Once accumulation over a predetermined number of frames is finished, the largest or maximum value among the accumulated correlator values is identified. If the maximum value exceeds a threshold, it will be declared as a peak and the address associated is the peak timing.

Abstract: In a DOCSIS based satellite gateway data is transmitted over a single downstream channel, at different throughput rates. Data destined for each subscriber/receiver is assigned a throughput rate depending upon the downstream signal quality of that subscriber/receiver. To accomplish this, the downstream DOCSIS MAC data is parsed to extract DOCSIS packets. The DOCSIS packets are then loaded into packet queues based on an identifier within such packets such as the MAC destination address or SID. Each of the queues represents a bandwidth efficiency or throughput rate that can be currently tolerated by specific subscribers based on the current signal quality being experienced at the subscriber location. A PHY-MAP describing the downstream data structure to be transmitted and inserted into the downstream data. Data is extracted from the packet queues in queue blocks as defined by the PHY-MAP.

Abstract: Herein described are at least a method and a system for implementing a high speed Tomlinson-Harashima Precoder. The method comprises using an L-tap transpose configuration of a Tomlinson-Harashima Precoder and processing a first discrete time sampled sequence using said L coefficients and L state variables by clocking the L-tap Tomlinson-Harashima Precoder using a clock signal wherein the clock signal has a clock rate equal to one half the symbol rate of the discrete time sampled sequence. In a representative embodiment, an L-tap Tomlinson-Harashima Precoder comprises a single integrated circuit chip, wherein the integrated circuit chip comprises at least one circuitry for processing a discrete time sampled sequence using L coefficients and L state variables by way of clocking the discrete time sampled sequence using a clock signal having a clock rate that is one half the symbol rate of the discrete time sampled sequence.