Abstract: A method for compiling and executing a nested loop includes initializing a nested loop controller with an outer loop count value and an inner loop count value. The nested loop controller includes a predicate FIFO. The method also includes coalescing the nested loop and, during execution of the coalesced nested loop, causing the nested loop controller to populate the predicate FIFO and executing a get predicate instruction having an offset value, where the get predicate returns a value from the predicate FIFO specified by the offset value. The method further includes predicating an outer loop instruction on the returned value from the predicate FIFO.

Abstract: A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.

Abstract: In an example, a system includes a processor, where the processor includes a plurality of processor registers, and where the processor is configured to execute a first instruction in a first execution context. The processor is also configured to receive a PRESERVE instruction that indicates at least one processor register among the plurality of processor registers. The processor is configured to, responsive to the PRESERVE instruction, preserve parameters in the at least one processor register and clear other processor registers in the plurality of processor registers in the first execution context. The processor is also configured to execute a second instruction in a second execution context.

Abstract: A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.

Abstract: A method of storing register data elements to interleave with data elements of a different register, a processor thereof, and a system thereof, wherein each non-consecutive data elements of a register is retrieved to be stored to interleave with each non-consecutive data elements of a different register upon an executive of an interleaving store instruction, wherein a mask instruction directing a lane of a storage space in which the non-consecutive data elements are stored is executed in conjunction with the interleaving store instruction, and wherein a processor of a second type is configured to emulate a processor of a first type to store the non-consecutive data elements the same as non-consecutive data elements stored in the first type processor.

Abstract: A method of storing register data elements to interleave with data elements of a different register, a processor thereof, and a system thereof, wherein each non-consecutive data elements of a register is retrieved to be stored to interleave with each non-consecutive data elements of a different register upon an executive of an interleaving store instruction, wherein a mask instruction directing a lane of a storage space in which the non-consecutive data elements are stored is executed in conjunction with the interleaving store instruction, and wherein a processor of a second type is configured to emulate a processor of a first type to store the non-consecutive data elements the same as non-consecutive data elements stored in the first type processor.

Abstract: A method for compiling and executing a nested loop includes initializing a nested loop controller with an outer loop count value and an inner loop count value. The nested loop controller includes a predicate FIFO. The method also includes coalescing the nested loop and, during execution of the coalesced nested loop, causing the nested loop controller to populate the predicate FIFO and executing a get predicate instruction having an offset value, where the get predicate returns a value from the predicate FIFO specified by the offset value. The method further includes predicating an outer loop instruction on the returned value from the predicate FIFO.

Abstract: A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.

Abstract: A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.

Abstract: A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.

Abstract: A method for compiling and executing a nested loop includes initializing a nested loop controller with an outer loop count value and an inner loop count value. The nested loop controller includes a predicate FIFO. The method also includes coalescing the nested loop and, during execution of the coalesced nested loop, causing the nested loop controller to populate the predicate FIFO and executing a get predicate instruction having an offset value, where the get predicate returns a value from the predicate FIFO specified by the offset value. The method further includes predicating an outer loop instruction on the returned value from the predicate FIFO.

Abstract: A method of storing register data elements to interleave with data elements of a different register, a processor thereof, and a system thereof, wherein each non-consecutive data elements of a register is retrieved to be stored to interleave with each non-consecutive data elements of a different register upon an executive of an interleaving store instruction, wherein a mask instruction directing a lane of a storage space in which the non-consecutive data elements are stored is executed in conjunction with the interleaving store instruction, and wherein a processor of a second type is configured to emulate a processor of a first type to store the non-consecutive data elements the same as non-consecutive data elements stored in the first type processor.

Abstract: A method for compiling and executing a nested loop includes initializing a nested loop controller with an outer loop count value and an inner loop count value. The nested loop controller includes a predicate FIFO. The method also includes coalescing the nested loop and, during execution of the coalesced nested loop, causing the nested loop controller to populate the predicate FIFO and executing a get predicate instruction having an offset value, where the get predicate returns a value from the predicate FIFO specified by the offset value. The method further includes predicating an outer loop instruction on the returned value from the predicate FIFO.

Abstract: A compiler converts a high level language program into a corresponding machine level language program. The compiler forms an initial control flow graph of the high level language program with nodes and edge, the nodes including a starting node, initializing a collapse count to zero, and sets the initial control flow graph as a current control flow graph. The compiler performs iterative collapsing operations on the current control flow graph until only a single node remains. After performing the iterative collapsing operations, data flow analysis is performed on the initial control flow graph for a number of iterations equal to one greater than the collapse count. Then, the machine level language program corresponding to the high level language program is generated based upon the data flow analysis.

Abstract: A compiler converts a human readable high level program into a corresponding machine language program. This invention improves data-flow analysis. A compiler implementing data-flow analysis typically relies on an iterative algorithm for data-flow analysis. According to the prior art determination of the exact number of loop iterations required for convergence was believed impractical. The prior art selected a maximum number of data-flow analysis iterations relatively arbitrarily. This invention calculates the number of iterations for convergence using backedges in a control flow graph of the source program. This permits the data-flow analysis to be run for exactly the number of iterations needed for convergence. In the event of convergence, an extra, useless iteration is avoided. In the event of non-convergence, valid data can be separated from invalid data, whereas all data was previously discarded.

Abstract: A shiftable memory is employed in a system and a method to shift a contiguous subset of stored data within the shiftable memory. The shiftable memory includes a memory having built-in shifting capability to shift a contiguous subset of data stored by the memory from a first location to a second location within the memory. The contiguous subset has a size that is smaller than a total size of the memory. The system further includes a processor to provide an address and the length of the contiguous subset. The method includes selecting the contiguous subset of data and shifting the selected contiguous subset.

Abstract: A computer system includes a processor and program storage coupled to the processor. The program storage stores a software instruction translator that, when executed by the processor, is configured to receive source code and translate the source code to a low-level language. The source code is restricted to a subset of a high-level language and the low-level language is a specialized instruction set. Each statement of the subset of the high-level language directly maps to an instruction of the low-level language.

Abstract: Embodiments of the present invention are directed to optoelectronic network switches. In one embodiment, an optoelectronic switch includes a set of roughly parallel input waveguides and a set of roughly parallel output waveguides positioned roughly perpendicular to the input waveguides. Each of the output waveguides crosses the set of input waveguides. The optoelectronic switch includes at least one switch element configured to switch one or more optical signals transmitted on one or more input waveguides onto one or more crossing output waveguides.

Abstract: Embodiments of the present invention are directed to implementing high-radix switch topologies on relatively lower-radix physical networks. In one embodiment, the method comprises constructing the physical network (702) composed of one or more optical switches connected via one or more waveguides. A desired switch topology (704) is then designed for implementation on the physical network. The switch topology is then overlain on the switch network by configuring the optical switches and waveguides (706) to implement the switch topology on the physical network. The optical switches can be reconfigured following a transmission over the physical network and can be configured to implement circuit switching or packet switch.

Abstract: Various embodiments of the present invention are directed to methods and systems for transmitting optical signals from a source to a plurality of receiving devices. In one method embodiment, an optical enablement signal is transmitted (401) from the source to the plurality of receiving devices. The target receiving device responds to receiving the optical enablement signal by preparing to receive one or more optical data signals. The source transmits the one or more optical data signals to the target receiving device. The remaining receiving devices do not receive the one or more optical data signals.