Abstract: The interconnection chip of the present invention is a custom chip which is designed to serve as an efficient link between system functional modules, such as arithmetic units, register files and input/output ports. The chip includes a crossbar interconnection, a FIFO or programmable delay for each of its inputs and a pipeline register file for each of its outputs. By using pre-stored control patterns, the chip can configure its crossbar and delays while performing other operations. Therefore, the usual functions of busses and register files can be realized with this single chip. Various embodiments and applications for the chip are disclosed.