Abstract: A method and apparatus is used to provide DC stabilization and noise reduction in a multistage power amplifier. The invention uses various feedback techniques to stabilize DC levels, which helps to reduce noise. The invention also uses other techniques to reduce noise, and to reduce the noise transfer function in a power amplifier.

Abstract: A method and apparatus provides an input structure for a power amplifier. In one example, the input structure has an input network and a predriver circuit to provide an input signal to the power amplifier. The input network includes a transformer for helping to maintain a constant input impedance. The predriver includes a limiting amplifier that provides isolation between the power amplifier and the RF input. A DC feedback circuit is used by the predriver that maintains the DC level of the inverters to a desired level.

Abstract: A method and apparatus provides an input structure for a power amplifier. In one example, the input structure has an input network and a predriver circuit to provide an input signal to the power amplifier. The input network includes a transformer for helping to maintain a constant input impedance. The predriver includes a limiting amplifier that provides isolation between the power amplifier and the RF input. A DC feedback circuit is used by the predriver that maintains the DC level of the inverters to a desired level.

Abstract: A method and apparatus is used to provide DC stabilization and noise reduction in a multistage power amplifier. The invention uses various feedback techniques to stabilize DC levels, which helps to reduce noise. The invention also uses other techniques to reduce noise, and to reduce the noise transfer function in a power amplifier.

Abstract: A data converter (10) includes an analog input element (12), an operational amplifier (14), a first reference input element (18), a second reference input element (22), and a control element (34). The analog input element (12) operably couples the analog signal to a first input (13) of the operational amplifier (14). The first and second reference input elements (18 & 22) respectively couple a first signal (16) and a second signal (22) to a first input of the operational amplifier (14). The control element (34) generates the control signal based on an output of the operational amplifier (14) to force the first input node (13) to be equivalent to the second input node (15) of the operational amplifier (14). The data converter (10) also includes an analog-to-digital converter (26) that allows the circuit to perform a sigma-delta conversion.

Abstract: An oscillator such as a pulled-crystal oscillator (50) provides low clock jitter by converting a sinusoidal voltage on a crystal's (51) terminals into a digital square wave with a comparator (56). The oscillating frequency of the crystal (51) is pulled by selectively switching in extra capacitance through capacitor digital-to-analog converters (CDACs) (57, 58). The oscillator (50) has built-in testability which allows individual capacitors in the CDACs (57, 58) to be quickly tested for opens. A scan path is connected to the inputs of the CDACs (57, 58) for selecting individual capacitors. A first input terminal of the comparator (56) is precharged before a capacitor under test (171) is connected. A comparison voltage is provided to the second input terminal.

Abstract: A low-power inverter (53) reduces power consumption over known inverter designs and is especially well-adapted for serving as a buffer in a Pierce crystal oscillator with a large load capacitance. The inverter (53) includes P- and N-side source-follower stages (310, 320) driving CMOS output transistor pairs (350, 360). The source followers are current-limited through current sources (311, 313, 321, 323) which are biased by a stable reference voltage such as a bandgap reference voltage. Clamping devices (331, 332) are provided to limit the voltages on the gates of the output transistors (350, 360), thereby limiting maximum currents thereof. In addition, a helper device (332) is connected to the gate of a P-channel output transistor (350). The P-channel output transistor (350) typically has a large gate area and thus a large capacitance, and the helper device (332) quickly increases the voltage at the gate when an input signal changes to a high voltage.

Abstract: An oscillator such as a pulled-crystal oscillator (50) provides low clock jitter by converting a sinusoidal voltage on a crystal's (51) terminals into a digital square wave with a comparator (56). The oscillating frequency of the crystal (51) is pulled by selectively switching in extra capacitance through capacitor digital-to-analog converters (CDACs) (57, 58). The oscillator (50) has built-in testability which allows individual capacitors in the CDACs (57, 58) to be quickly tested for opens. A scan path is connected to the inputs of the CDACs (57, 58) for selecting individual capacitors. A first input terminal of the comparator (56) is precharged before a capacitor under test (171) is connected. A comparison voltage is provided to the second input terminal.

Abstract: A frequency synthesizer circuit (10). Circuit (10) has a counter (12), a latch/decoder (14), a divider (16), and an optional wave shaper (18) which synthesize an output clock signal X. Counter (12) counts a number of clock signal N periods that occur within one clock signal M period and this count is stored as a count value. The count value is latched and/or decoded by the latch/decoder (14) to produce a divisor which is output from the latch/decoder (14) to the divider (16). The divider (16) divides a clock signal N frequency by the divisor to provide a spiked waveform to the wave shaper (18). The wave shaper (18) alters a frequency and/or a duty cycle of the spiked waveform to produce the clock signal X. Clock signal X has a substantially constant frequency regardless of the clock signal N frequency or operational variation in the system clock N frequency.

Abstract: Time multiplexing two or more current sources to source current to a single bipolar transistor achieves a more stable Vbe input for a switched capacitor bandgap reference circuit. With the proper selection of switched capacitor sizes and current sources values to establish a Vbe voltage at the input of a differential amplifier, an output reference voltage can be achieved that is substantially independent of processing and temperature variations as well as circuit aging characteristics. The invention reduces, and in some cases, eliminates the need for trimming values of capacitance or resistance to achieve the desired output reference voltage.

Abstract: A single-ended input to differential output amplifier performs a predetermined transfer function on an input signal substantially independently of nonlinearities in component values. The input signal and a first reference voltage are coupled to a circuit network, which is coupled to a fully differential operational amplifier, to implement the predetermined transfer function. A common mode voltage between positive and negative output signals of the operational amplifier is sensed and fed back to the operational amplifier so that the operational amplifier may set the common mode voltage to a second reference voltage. The circuit network has first, second, and third capacitors, the third capacitor coupled between a positive input terminal and the first reference voltage.

Abstract: A current source circuit providing a constant output for wide variations in supply voltages is achieved by creating a constant reference current by reflecting the difference in the base to emitter voltage of two bipolar transistors across a resistor. A first current mirror creates an equal current which flows through two diode connected transistors that produce an output voltage proportional to the current flowing through them. This current also flows through a second current mirror which creates an equal current to flow to a feedback connection. The feedback connection adjusts the base voltage of the two bipolar transistors until a current equal to the reference current flows in a third current mirror. The current flowing in this third current mirror is also applied to the feedback connection to insure that all currents remain equal thereby insuring the output remains constant.

Abstract: A CMOS circuit having a differential input stage which provides a single output is provided. An output stage has a capacitor which is used as a Miller integrator coupled thereto for frequency stabilization. A cascode portion is coupled to the Miller integrator to maintain one of the capacitor's electrodes at a predetermined voltage potential. A compensation portion is coupled to the cascode portion to compensate for power supply induced errors created when either an N-channel transistor in an N-well process or a P-channel transistor in a P-well process is used in the cascode portion.

Abstract: An analog two pole filter is provided which uses a single amplifier to implement a predetermined transfer function. The filter has a differential input and converts the two inputs to a single output utilizing the same amplifier which performs the filtering function. By coupling a capacitor across the differential input and utilizing the differential aspect of the input signals, the capacitor may be implemented with half the capacitance otherwise required to implement the predetermined transfer function, thereby minimizing circuit area.

Abstract: A power amplifier particularly useful as a line driver operating at low power supply voltages is provided. An input portion comprising a differential input configuration is coupled to an output stage having a P-channel MOS transistor connected in series with an N-channel MOS transistor between two power supply voltage terminals. A control portion is coupled to both the input portion and the output stage for providing first and second control signals to the output portion. The control portion regulates the output quiescent current at a predetermined value independent of signal amplification provided by the input portion. The output signal can swing substantially between two power supply voltage potentials.

Abstract: A circuit which converts differential outputs of a fully differential amplifier to a single output using a buffer amplifier is provided. The fully differential amplifier has common-mode feedback provided by a differential feedback stage. An input of the common-mode differential feedback stage is connected to a predetermined one of the differential outputs to maintain the predetermined output at a reference voltage potential. The buffer amplifier uses diffused or well resistors and a single-ended differential amplifier. The buffer amplifier has a balanced structure which minimizes noise and resistor nonlinearity output errors. The circuit also maintains excellent power supply rejection.

Abstract: A fully differential amplifier which is compensated for both input offset voltage error and output common-mode variation is provided. The differential amplifier provides two very accurate output reference voltages which vary in proportion to the difference between first and second input voltages. In one form, the differential amplifier functions as an integrator. A differential amplifier is provided which uses first and second input pairs of differential transistors for normal differential operation and for common-mode output voltage regulation, respectively. Both input pairs of transistors must be compensated for offset voltage associated therewith. A compensation portion external to the differential amplifier is used to compensate for an offset voltage associated with circuitry within the differential amplifier for regulating the common-mode output voltage.

Abstract: An input structure which is parasitic insensitive and allows a fully differential amplifier to receive a single input voltage while maintaining a predetermined common-mode input voltage is provided. A single input voltage is charged onto two capacitors which are coupled in series between the input voltage and a predetermined common-mode reference voltage terminal during a first time period. During a second time period, the two capacitors are reconfigured so that each capacitor is connected between the reference voltage terminal and a predetermined one of the inputs of the fully differential amplifier. Due to the balanced nature of the input structure, all parasitic capacitance error terms are rejected by the differential amplifier.

Abstract: A switched capacitor integrator for receiving a single input signal is compensated for parasitic capacitance errors with a minimum amount of circuitry. Although a single-ended amplifier is provided, a differential amplifier input is used which receives equal amounts of parasitic charge to effectively cancel charge errors. The size of the compensating capacitive circuitry may be reduced by making the input parasitic capacitance at one of the inputs proportionately larger so that the noise gain in both positive and negative signal paths remains substantially the same.