Abstract: A model of a finite state machine suited for implementation in a microcomputer includes logical specifications stored in memory which determine whether a change of outputs should be effected in response to predetermined combinations of input parameters and whether a change of state should be effected based on stored logical conditions of input parameters. Additional control of the flow of the steps of the finite state machine are under the control of the designer wherein a designer controlled variable permits a selection following a state transition as to whether or not an immediate test or input parameters will be made to determine whether additional actions are required or whether a return to a determination of state transition is to be made.

Abstract: A set of indexes associated with each state of the finite state machine provides an address locator to a location in memory of a microprocessor where sets of logical vectors are stored. A count stored in a group of logical vectors identifies the number of stored logical vectors and hence, permits memory allocation to vary depending upon the number of logical conditions to be applied for a given test. A predetermined null value entered in an index is interpreted by the finite state machine as requiring no further processing and having no corresponding memory allocated for logical vectors.

Abstract: Conventional AND vectors are compared to corresponding input vectors of the same length as part of the logic processing associated with the finite state machine. AND vectors having a single set bit are translated into AND index vectors in which the bit position of the single set bit is encoded. AND index vectors are also identified by an index flag. The encoded bit position is utilized to identify the corresponding bit position in the input vector to perform a TRUE/FALSE test to determine an overall TRUE or FALSE indication. This technique avoids a bit by bit comparison for AND vectors having a single set bit.