Abstract: The present disclosure is related to methods, systems, and machine-readable media for interference attenuation of a residual portion of seismic data, such as may be recorded in a marine seismic survey. Recorded seismic data can be separated into a portion attributed to a source and a residual portion. Seismic interference attenuation can be performed on the residual portion.

Abstract: The present disclosure is related to methods, systems, and machine-readable media for interference attenuation of a residual portion of seismic data, such as may be recorded in a marine seismic survey. Recorded seismic data can be separated into a portion attributed to a source and a residual portion. Seismic interference attenuation can be performed on the residual portion.

Abstract: The present disclosure is related to methods, systems, and machine-readable media for interference attenuation of a residual portion of seismic data, such as may be recorded in a marine seismic survey. Recorded seismic data can be separated into a portion attributed to a source and a residual portion. Seismic interference attenuation can be performed on the residual portion.

Abstract: The present disclosure is related to methods, systems, and machine-readable media for interference attenuation of a residual portion of seismic data, such as may be recorded in a marine seismic survey. Recorded seismic data can be separated into a portion attributed to a source and a residual portion. Seismic interference attenuation can be performed on the residual portion.

Abstract: A multiple ramp analogue-to-digital converter comprises an integrator connected to receive and integrate an analogue input signal to be converted, and an opposing coarse reference signal. Instead of these signals being applied to the integrator sequentially, as is conventional, they are applied simultaneously. A flash converter is used to provide a rough initial estimate of the magnitude and polarity of the analogue input signal, so that the duration of application of the coarse reference signal can be estimated in advance. A fine reference signal is then applied to the integrator to restore its output to zero and improve the resolution of the conversion.

Abstract: In a frequency response analyzer capable of testing a system under test at a higher frequency F derived from a signal generator providing a relatively higher frequency F/K. A reference signal of frequency F-C is supplied to a mixer where it is multiplied with the return signal of frequency F to provide a fixed frequency output C. An analyzing portion of the frequency response analyzer is therefore required to operate only at this fixed frequency C and may provide an output in any suitable form, for example displays of magnitude and phase against frequency as F/K is varied. The present invention overcomes the problem of providing a VCO based signal generator capable of operation at very low frequencies.

Abstract: In apparatus for performing frequency response analysis of a system under test to establish response coefficients at various frequencies, a look up Read Only Memory is sequentially addressed to give a driving signal. The signal received from a system under test is fed to the analogue input of a multiplying digital to analogue converter, the digital input being fed from a Read Only Memory, storing values of a reference waveform (e.g., sin wt), by which the received signal is multiplied. The integration period of the multiplying digital to analogue converter is selected such that unwanted multiplication products integrate out, leaving the response coefficient at the reference frequency. For speed, a second channel may be used to establish the orthogonal coefficient. Methods are proposed so that the arrangement operates with single or two quadrant multiplying digital to analogue converters and to select harmonic coefficients.

Abstract: In a frequency response analyser for operation at high frequencies a signal of frequency F for application to a system under test (15) is generated from a frequency synthesizer (11) capable of operation only at a relatively lower frequency F/K by generating a first signal (19) of frequency at the relatively lower frequency F/K by generating a second signal 104 at the relatively higher frequency (f+F) and generating a third signal (at 114) or F(1--1/K). The second signal is applied to the system under test and an output signal (at 16) derived therefrom. The output is multiplied by the third signal to provide a product signal, and the product signal is analyzed with respect to first signal by means of a correlator 14. The present invention overcomes the limitation in maximum testing frequency imposed by the frequency synthesizers of prior art frequency response analyzers.

Abstract: In a heterodyning arrangement to enable frequency response testing of a system at a high frequency F using a digital correlator capable of operation at a lower frequency F/h, an offset signal is generated at a frequency F(h-1)/h and multiplied with the output signal of the system under test. Two heterodynes result: a wanted signal at a frequency F/h, and an unwanted image signal at F(2h-1)/h. The value of h is selectable independently of a divisor N which controls derivation of the test frequency F from a frequency synthesizer operating at a frequency NF. Thus the frequency of the image signal can be arranged to avoid spurious non-zero responses in the digital correlation process at frequencies related to N.

Abstract: A rectifying circuit comprises a high gain A.C. amplifier having first and second rectifying means connected in respective negative feedback paths between its output and its input and arranged to pass respective feedback currents of opposite polarity. A current copying device is responsive to the current flowing in one of the rectifying means to copy this current.In a preferred embodiment, said one rectifying means comprises the base-emitter junction of a first transistor, whose collector is connected to the input of the amplifier, and the current copying means comprises a second transistor, matched with the first transistor, and having its base-emitter junction connected in parallel with the base-emitter junction of the first transistor. The rectified output signal in this embodiment is taken from the free collector of the second transistor.

Abstract: In a DVOM of the dual slope type, an unknown resistance or conductance to be measured is connected to a reference signal source to generate a voltage or current which is measured by the DVOM. However, if the input impedance of the DVOM is not extremely high, it loads the unknown resistance or conductance, and renders the relationship between the value of the unknown resistance or conductance and the actual voltage or current measured by the DVOM non-linear. In order to correct for this, a proportion of this actual voltage or current is algebraically summed with the reference signal used in the DVOM for generating the second slope of its dual slope operation, the proportion being selected in dependence on the input impedance of the DVOM (which can thus now take any convenient value) to linearize the relationship between the value of the unknown resistance or conductance and the output signal of the DVOM.

Abstract: A bipolar reference voltage source comprises first and second ratio-matched transistors having respective collector load resistors and arranged to pass slightly different currents. The emitter of the first transistor is connected to two emitter resistors in series, while the emitter of the second is connected to the junction between the emitter resistors. The bases of the transistors are commoned, while their collectors are respectively connected to the two inputs of a differential amplifier. A switching arrangement has a first state in which the output of the differential amplifier is connected to the bases of the transistors, and the end of the two emitter resistors remote from the transistors is grounded, thereby producing a first reference voltage of one polarity at the output of the differential amplifier.