Abstract: A monolithic integrated circuit for providing enhanced audio performance in personal computers. The monolithic circuit includes a wavetable synthesizer; a full function stereo coding and decoding circuit including analog-to-digital and digital-to-analog conversion; data compression, and mixing and muxing of analog signals; a local memory control module for interfacing with external memory; a game-MIDI port module; a system bus interface; and a control module for compatibility and circuit control functions.

Abstract: A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44.1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data.

Abstract: The present invention is an interface adapter circuit that allows multiple types of 256K by 16 bit dynamic random random access memories to be used by system manufacturers. The interface adapter circuit selects a type of outputs signal set to produce responsive to a mode selection signal. The circuit converts an input signal set including a column address probe and low and high by write signals into either a first output signal set, including one column address strobe and high and low byte write signals, or a second output signal set including a single write signal and high and low column address signals, responsive to the selection signal. The circuit includes a logic circuit for producing the signals and flip flops for holding the signal produced. The flip flops also synchronize other memory address, etc. signals with the signals produced by the adapter circuit.