Abstract: The present invention relates to a DC power supply of the free-running flyback type and a current limit circuit incorporated therein. The current limit is changed as a function of AC line voltage thereby reducing the worst case peak power dissipation in the power switching transistor. In one embodiment, one or more turns on the transformer provides a sensing voltage proportional to supply voltage to vary the switching transistor current limit as a function of supply voltage.

Abstract: A switching rectifier power supply circuit has a power MOS transistor connected in series with half of the primary of a center-tapped transformer, and has rectifiers in series with an inductive load on the secondary side. The gate of the power transistor is driven by a pulse source which is pulse-width modulated in response to the load voltage, and also controlled in response to the current through the power transistor. To prevent leading-edge current spikes due to turn-on of the power transistor from adversely affecting the pulse-width modulator, yet allow trailing-edge current spikes due to transformer saturation to be compensated for, an inhibit circuit is included in the control path responding to current through the power transformer.

Abstract: A synchronous rectifier power supply circuit has a pair of power MOS transistors connected in series with the primary and secondary of a transformer, respectively, and another power MOS transistor connected across an inductive load on the secondary side. The gates of the pair of transistors are driven by a pulse source which is pulse-width modulated in response to the load voltage, and the other transistor has its gate driven by the inverse of the pulse source. To prevent current spikes and power losses due to the pair of transistors being on during a transition period at the same time the other transistor is on, a high-gain bistable logic circuit is used to drive the gates; A NOR gate prevent the gate of the other transistor from rising to a turn-on voltage until the gates of the pair of transistors are at below a turn-on voltage. A second NOR gate prevents the gates of the pair of transistors from reaching a turn-on voltage until the gate of the other transistor is below a turn-on voltage.